The I2C Controller is available in VHDL and is optimized for the Altera® APEX™ , Stratix® , and Cyclone™ device families. All of the register addresses are defined as constants in the VHDL source files and can be easily customized for customer use. The MBASE address is defined as a generic and can also be easily changed and customized for customer use. In addition, this design outputs the MCF signal on a pin which can be used by the uC as a quick indication that the I2C transfer is complete. This design uses the I2C SCL signal as a clock. This requires that the SCL signal have clean, fast edges on both the rising and falling edges of this signal. Slow rise and fall times on this signal can show noise effects which can cause improper clocking of registers within the Stratix FPGA. If the loading of the SCL signal in the system is such that the rise and fall times are slow (>20nS), external buffers such as Schmitt Triggers will be required to interface to the

I2C Controller Reference Design.doc
I2C总线代码使用手册.doc
license.txt
qii
...\cmp_state.ini
...\db
...\..\cntr_4q7.tdf
...\..\cntr_pd8.tdf
...\..\cntr_re8.tdf
...\..\i2c.asm.qmsg
...\..\i2c.cmp.cdb
...\..\i2c.cmp.ddb
...\..\i2c.cmp.hdb
...\..\i2c.cmp.rdb
...\..\i2c.cmp.tdb
...\..\i2c.cmp0.ddb
...\..\i2c.db_info
...\..\i2c.eco.cdb
...\..\i2c.eda.qmsg
...\..\i2c.fit.qmsg
...\..\i2c.hier_info
...\..\i2c.hif
...\..\i2c.icc
...\..\i2c.map.cdb
...\..\i2c.map.hdb
...\..\i2c.map.qmsg
...\..\i2c.pre_map.cdb
...\..\i2c.pre_map.hdb
...\..\i2c.psp
...\..\i2c.rpp.qmsg
...\..\i2c.rtlv.hdb
...\..\i2c.rtlv_sg.cdb
...\..\i2c.rtlv_sg_swap.cdb
...\..\i2c.sgate.rvd
...\..\i2c.sgdiff.cdb
...\..\i2c.sgdiff.hdb
...\..\i2c.signalprobe.cdb
...\..\i2c.sld_design_entry.sci
...\..\i2c.sld_design_entry_dsc.sci
...\..\i2c.syn_hier_info
...\..\i2c.tan.qmsg
...\..\i2c_cmp.qrpt
...\..\i2c_hier_info
...\..\i2c_sim.qrpt
...\..\i2c_syn_hier_info
...\i2c.asm.rpt
...\i2c.done
...\i2c.eda.rpt
...\i2c.fit.eqn
...\i2c.fit.rpt
...\i2c.fit.summary
...\i2c.flow.rpt
...\i2c.map.eqn
...\i2c.map.rpt
...\i2c.map.summary
...\i2c.pin
...\i2c.pof
...\i2c.qpf
...\i2c.qsf
...\i2c.qws
...\i2c.sof
...\i2c.tan.rpt
...\i2c.tan.summary
...\i2c_assignment_defaults.qdf
...\quartus_nativelink_simulation.log
...\simulation
...\..........\modelsim
...\..........\........\i2c.vo
...\..........\........\i2c_modelsim.xrf
...\..........\........\i2c_v.sdo
...\..........\........\modelsim.ini
...\..........\........\modelsim_work
...\..........\........\.............\0modelsim_work.mgf
...\..........\........\.............\1modelsim_work.mgf
...\..........\........\.............\3modelsim_work.mgf
...\..........\........\.............\4modelsim_work.mgf
...\..........\........\.............\modelsim_work.lib
...\..........\........\.............\vcp.epr
...\..........\........\.............\vcp_cmd.log
...\..........\........\vsimsa.cfg
...\..........\vcs
...\..........\...\i2c.vo
...\..........\...\i2c_v.sdo
read_me.doc
read_me.txt
soc
...\i2c.vhd
...\i2c.vhd.bak
...\i2c_control.vhd
...\shift.vhd
...\uc_interface.vhd
...\upcnt4.vhd
testbench
.........\micro_master_tb.vhd
.........\micro_slave_tb.vhd
.........\micro_tb.vhd
.........\micro_test.do
.........\micro_test.vhd
.........\micro_test_post.do
.........\micro_test_post.vhd

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