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digitron

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2015-12-13
  • Size : 460kb
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  • Author :木***
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Introduction - If you have any usage issues, please Google them yourself
Digital display, which contains the source code and many other top level schematics decoder circuit and finally a combination.
Packet file list
(Preview for download)


3_2
...\counter4
...\........\counter4.bdf
...\........\counter4.done
...\........\counter4.flow.rpt
...\........\counter4.map.rpt
...\........\counter4.map.summary
...\........\counter4.qpf
...\........\counter4.qsf
...\........\counter4.qws
...\........\counter4.sim.rpt
...\........\counter4.vwf
...\........\db
...\........\..\counter4.cbx.xml
...\........\..\counter4.cmp.rdb
...\........\..\counter4.db_info
...\........\..\counter4.eco.cdb
...\........\..\counter4.eds_overflow
...\........\..\counter4.fnsim.cdb
...\........\..\counter4.fnsim.hdb
...\........\..\counter4.fnsim.qmsg
...\........\..\counter4.hier_info
...\........\..\counter4.hif
...\........\..\counter4.lpc.html
...\........\..\counter4.lpc.rdb
...\........\..\counter4.lpc.txt
...\........\..\counter4.map.cdb
...\........\..\counter4.map.hdb
...\........\..\counter4.map.logdb
...\........\..\counter4.map.qmsg
...\........\..\counter4.pre_map.cdb
...\........\..\counter4.pre_map.hdb
...\........\..\counter4.rtlv.hdb
...\........\..\counter4.rtlv_sg.cdb
...\........\..\counter4.rtlv_sg_swap.cdb
...\........\..\counter4.sgdiff.cdb
...\........\..\counter4.sgdiff.hdb
...\........\..\counter4.sim.cvwf
...\........\..\counter4.sim.hdb
...\........\..\counter4.sim.qmsg
...\........\..\counter4.sim.rdb
...\........\..\counter4.simfam
...\........\..\counter4.sld_design_entry.sci
...\........\..\counter4.sld_design_entry_dsc.sci
...\........\..\counter4.syn_hier_info
...\........\..\counter4.tis_db_list.ddb
...\........\..\counter4.tmw_info
...\........\..\prev_cmp_counter4.qmsg
...\........\..\prev_cmp_counter4.sim.qmsg
...\........\..\wed.wsf
...\........\incremental_db
...\........\..............\compiled_partitions
...\........\..............\...................\counter4.root_partition.map.kpt
...\........\..............\README
...\decoder2_3
...\..........\db
...\..........\..\decoder2_3.cbx.xml
...\..........\..\decoder2_3.cmp.rdb
...\..........\..\decoder2_3.db_info
...\..........\..\decoder2_3.eco.cdb
...\..........\..\decoder2_3.eds_overflow
...\..........\..\decoder2_3.fnsim.cdb
...\..........\..\decoder2_3.fnsim.hdb
...\..........\..\decoder2_3.fnsim.qmsg
...\..........\..\decoder2_3.hier_info
...\..........\..\decoder2_3.hif
...\..........\..\decoder2_3.lpc.html
...\..........\..\decoder2_3.lpc.rdb
...\..........\..\decoder2_3.lpc.txt
...\..........\..\decoder2_3.map.cdb
...\..........\..\decoder2_3.map.hdb
...\..........\..\decoder2_3.map.logdb
...\..........\..\decoder2_3.map.qmsg
...\..........\..\decoder2_3.pre_map.cdb
...\..........\..\decoder2_3.pre_map.hdb
...\..........\..\decoder2_3.rtlv.hdb
...\..........\..\decoder2_3.rtlv_sg.cdb
...\..........\..\decoder2_3.rtlv_sg_swap.cdb
...\..........\..\decoder2_3.sgdiff.cdb
...\..........\..\decoder2_3.sgdiff.hdb
...\..........\..\decoder2_3.sim.cvwf
...\..........\..\decoder2_3.sim.hdb
...\..........\..\decoder2_3.sim.qmsg
...\..........\..\decoder2_3.sim.rdb
...\..........\..\decoder2_3.simfam
...\..........\..\decoder2_3.sld_design_entry.sci
...\..........\..\decoder2_3.sld_design_entry_dsc.sci
...\..........\..\decoder2_3.syn_hier_info
...\..........\..\decoder2_3.tis_db_list.ddb
...\..........\..\decoder2_3.tmw_info
...\..........\..\prev_cmp_decoder2_3.qmsg
...\..........\..\wed.wsf
...\..........\decoder2_3.bdf
...\..........\decoder2_3.done
...\..........\decoder2_3.flow.rpt
...\..........\decoder2_3.map.rpt
...\..........\decoder2_3.map.summary
...\..........\decoder2_3.qpf
...\..........\decoder2_3.qsf
...\..........\decoder2_3.qws
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