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  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-12-14
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Introduction - If you have any usage issues, please Google them yourself
code to implement the FIR function on zedboard
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lab6\fir.c
....\fir.h
....\fir_coef.dat
....\....ip\component.xml
....\......\fir_ip.data\constrs_1\fileset.xml
....\......\...........\sim_1\fileset.xml
....\......\...........\.ources_1\fileset.xml
....\......\...........\wt\java_command_handlers.wdf
....\......\...........\..\project.wpc
....\......\...........\..\webtalk_pa.xml
....\......\fir_ip.filter
....\......\.......srcs\sources_1\imports\verilog\fir.v
....\......\...........\.........\.......\.......\fir_ap_rst_if.v
....\......\...........\.........\.......\.......\fir_c.v
....\......\...........\.........\.......\.......\fir_c_rom.dat
....\......\...........\.........\.......\.......\fir_io_if.v
....\......\...........\.........\.......\.......\fir_shift_reg.v
....\......\...........\.........\.......\.......\fir_shift_reg_ram.dat
....\......\...........\.........\.......\.......\fir_top.v
....\......\fir_ip.xpr
....\......\....top_0\fir_top_0.xci
....\......\.........\fir_top_0.xml
....\......\........._0\fir_top_0.xci
....\......\...........\fir_top_0.xml
....\......\xgui\fir_top_v1_0.tcl
....\lab6.c
....\xfir_fir_io.h
....\fir_ip\fir_ip.srcs\sources_1\imports\verilog
....\......\...........\.........\imports
....\......\.......cache\compile_simlib
....\......\.......data\constrs_1
....\......\...........\sim_1
....\......\...........\sources_1
....\......\...........\wt
....\......\.......srcs\sources_1
....\......\fir_ip.cache
....\......\fir_ip.data
....\......\fir_ip.srcs
....\......\fir_top_0
....\......\fir_top_0_0
....\......\xgui
....\fir_ip
lab6
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