verilog hdl BCD to 7seg converter with testing module

MTM_UEC1_lab04_raportfinalny.pdf
wyswietlacz7seg\wyswietlacz7seg.cache
...............\.....................\compile_simlib
...............\.....................\wt
...............\.....................\..\java_command_handlers.wdf
...............\.....................\..\synthesis.wdf
...............\.....................\..\synthesis_details.wdf
...............\.....................\..\webtalk_pa.xml
...............\.....................\..\xsim.wdf
...............\wyswietlacz7seg.runs
...............\....................\impl_1
...............\....................\......\.init_design.begin.rst
...............\....................\......\.init_design.end.rst
...............\....................\......\.opt_design.begin.rst
...............\....................\......\.opt_design.end.rst
...............\....................\......\.place_design.begin.rst
...............\....................\......\.place_design.end.rst
...............\....................\......\.route_design.begin.rst
...............\....................\......\.route_design.end.rst
...............\....................\......\.vivado.begin.rst
...............\....................\......\.vivado.end.rst
...............\....................\......\.Vivado_Implementation.queue.rst
...............\....................\......\.write_bitstream.begin.rst
...............\....................\......\.write_bitstream.end.rst
...............\....................\......\.Xil
...............\....................\......\artix7_bcd.bit
...............\....................\......\artix7_bcd.tcl
...............\....................\......\artix7_bcd.vdi
...............\....................\......\artix7_bcd_3916.backup.vdi
...............\....................\......\artix7_bcd_clock_utilization_placed.rpt
...............\....................\......\artix7_bcd_control_sets_placed.rpt
...............\....................\......\artix7_bcd_drc_opted.rpt
...............\....................\......\artix7_bcd_drc_routed.pb
...............\....................\......\artix7_bcd_drc_routed.rpt
...............\....................\......\artix7_bcd_io_placed.rpt
...............\....................\......\artix7_bcd_opt.dcp
...............\....................\......\artix7_bcd_placed.dcp
...............\....................\......\artix7_bcd_power_routed.rpt
...............\....................\......\artix7_bcd_power_summary_routed.pb
...............\....................\......\artix7_bcd_route_status.pb
...............\....................\......\artix7_bcd_route_status.rpt
...............\....................\......\artix7_bcd_routed.dcp
...............\....................\......\artix7_bcd_timing_summary_routed.rpt
...............\....................\......\artix7_bcd_timing_summary_routed.rpx
...............\....................\......\artix7_bcd_utilization_placed.pb
...............\....................\......\artix7_bcd_utilization_placed.rpt
...............\....................\......\gen_run.xml
...............\....................\......\htr.txt
...............\....................\......\init_design.pb
...............\....................\......\ISEWrap.js
...............\....................\......\ISEWrap.sh
...............\....................\......\opt_design.pb
...............\....................\......\place_design.pb
...............\....................\......\project.wdf
...............\....................\......\route_design.pb
...............\....................\......\rundef.js
...............\....................\......\runme.bat
...............\....................\......\runme.log
...............\....................\......\runme.sh
...............\....................\......\vivado.jou
...............\....................\......\vivado.pb
...............\....................\......\vivado_3916.backup.jou
...............\....................\......\write_bitstream.pb
...............\....................\synth_1
...............\....................\.......\.vivado.begin.rst
...............\....................\.......\.vivado.end.rst
.........

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