Written in Verilog language transfer binary BCD code, can be used as a teaching experiment or the homework, a complete project code

二进制转BCD码\bcd.asm.rpt
.............\bcd.cdf
.............\bcd.done
.............\bcd.fit.eqn
.............\bcd.fit.rpt
.............\bcd.fit.summary
.............\bcd.flow.rpt
.............\bcd.map.eqn
.............\bcd.map.rpt
.............\bcd.map.summary
.............\bcd.pin
.............\bcd.pof
.............\bcd.qpf
.............\bcd.qsf
.............\bcd.qws
.............\bcd.tan.rpt
.............\bcd.tan.summary
.............\bcd.vhd
.............\bcd.vhd.bak
.............\bcd_assignment_defaults.qdf
.............\cmp_state.ini
.............\db\add_sub_5ph.tdf
.............\..\bcd.asm.qmsg
.............\..\bcd.cbx.xml
.............\..\bcd.cmp.cdb
.............\..\bcd.cmp.hdb
.............\..\bcd.cmp.logdb
.............\..\bcd.cmp.rdb
.............\..\bcd.cmp.tdb
.............\..\bcd.cmp0.ddb
.............\..\bcd.db_info
.............\..\bcd.eco.cdb
.............\..\bcd.fit.qmsg
.............\..\bcd.hier_info
.............\..\bcd.hif
.............\..\bcd.map.cdb
.............\..\bcd.map.hdb
.............\..\bcd.map.logdb
.............\..\bcd.map.qmsg
.............\..\bcd.pre_map.cdb
.............\..\bcd.pre_map.hdb
.............\..\bcd.rtlv.hdb
.............\..\bcd.rtlv_sg.cdb
.............\..\bcd.rtlv_sg_swap.cdb
.............\..\bcd.sgdiff.cdb
.............\..\bcd.sgdiff.hdb
.............\..\bcd.sld_design_entry.sci
.............\..\bcd.sld_design_entry_dsc.sci
.............\..\bcd.syn_hier_info
.............\..\bcd.tan.qmsg
.............\..\bcd.tis_db_list.ddb
.............\..\bcd.tmw_info
.............\..\bcd_cmp.qrpt
.............\..\prev_cmp_bcd.map.qmsg
.............\..\prev_cmp_bcd.qmsg
.............\db
二进制转BCD码

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