DDS source FPGA-based design 1. The output signal is a sine wave, triangle spread pulse 2. The signal amplitude adjustable range: 1V ~ 5V 3. AM step: 10mV The signal frequency is low frequency: 10HZ ~ 1MHZ 5. Frequency adjustment step 10HZ ~ 100HZ frequency of 1HZ, 100HZ ~ 1kHZ band is 10HZ, 1KHZ ~ 1MHZ band is 100HZ 6. Frequency adjustment mode through the keyboard input 7. The use of LCD display type signal, amplitude, frequency step size, step AM

ZX_SOPC0
........\.sopc_builder
........\.............\filters.xml
........\.............\preferences.xml
........\Adder.bsf
........\Adder.qip
........\Adder.v
........\cpu.sdc
........\cpu.v
........\cpu_jtag_debug_module_sysclk.v
........\cpu_jtag_debug_module_tck.v
........\cpu_jtag_debug_module_wrapper.v
........\cpu_ociram_default_contents.mif
........\cpu_oci_test_bench.v
........\cpu_rf_ram_a.mif
........\cpu_rf_ram_b.mif
........\cpu_test_bench.v
........\db
........\..\add_sub_5oj.tdf
........\..\altsyncram_0a02.tdf
........\..\altsyncram_2bf1.tdf
........\..\altsyncram_3bf1.tdf
........\..\altsyncram_d7a1.tdf
........\..\altsyncram_f3a1.tdf
........\..\altsyncram_f572.tdf
........\..\altsyncram_oda1.tdf
........\..\altsyncram_r1m1.tdf
........\..\altsyncram_sc31.tdf
........\..\altsyncram_t0a1.tdf
........\..\a_dpfifo_q131.tdf
........\..\a_fefifo_7cf.tdf
........\..\cntr_1ob.tdf
........\..\cntr_do7.tdf
........\..\dpram_nl21.tdf
........\..\logic_util_heursitic.dat
........\..\mux_qsc.tdf
........\..\PLL100M_altpll.v
........\..\prev_cmp_ZX_SOPC.qmsg
........\..\scfifo_jr21.tdf
........\..\ZX_SOPC.amm.cdb
........\..\ZX_SOPC.asm.qmsg
........\..\ZX_SOPC.asm.rdb
........\..\ZX_SOPC.asm_labs.ddb
........\..\ZX_SOPC.cbx.xml
........\..\ZX_SOPC.cmp.bpm
........\..\ZX_SOPC.cmp.cdb
........\..\ZX_SOPC.cmp.hdb
........\..\ZX_SOPC.cmp.kpt
........\..\ZX_SOPC.cmp.logdb
........\..\ZX_SOPC.cmp.rdb
........\..\ZX_SOPC.cmp_merge.kpt
........\..\ZX_SOPC.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
........\..\ZX_SOPC.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd
........\..\ZX_SOPC.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
........\..\ZX_SOPC.db_info
........\..\ZX_SOPC.eda.qmsg
........\..\ZX_SOPC.fit.qmsg
........\..\ZX_SOPC.hier_info
........\..\ZX_SOPC.hif
........\..\ZX_SOPC.idb.cdb
........\..\ZX_SOPC.lpc.html
........\..\ZX_SOPC.lpc.rdb
........\..\ZX_SOPC.lpc.txt
........\..\ZX_SOPC.map.bpm
........\..\ZX_SOPC.map.cdb
........\..\ZX_SOPC.map.hdb
........\..\ZX_SOPC.map.kpt
........\..\ZX_SOPC.map.logdb
........\..\ZX_SOPC.map.qmsg
........\..\ZX_SOPC.map_bb.cdb
........\..\ZX_SOPC.map_bb.hdb
........\..\ZX_SOPC.map_bb.logdb
........\..\ZX_SOPC.pre_map.cdb
........\..\ZX_SOPC.pre_map.hdb
........\..\ZX_SOPC.rtlv.hdb
........\..\ZX_SOPC.rtlv_sg.cdb
........\..\ZX_SOPC.rtlv_sg_swap.cdb
........\..\ZX_SOPC.sgdiff.cdb
........\..\ZX_SOPC.sgdiff.hdb
........\..\ZX_SOPC.sld_design_entry.sci
........\..\ZX_SOPC.sld_design_entry_dsc.sci
........\..\ZX_SOPC.smart_action.txt
........\..\ZX_SOPC.sta.qmsg
........\..\ZX_SOPC.sta.rdb
........\..\ZX_SOPC.sta_cmp.8_slow_1200mv_85c.tdb
........\..\ZX_SOPC.syn_hier_info
........\..\ZX_SOPC.tiscmp.fastest_slow_1200mv_0c.ddb
........\..\ZX_SOPC.tiscmp.fastest_slow_1200mv_85c.ddb
........\..\ZX_SOPC.tiscmp.fast_1200mv_0c.ddb
........\..\ZX_SOPC.tiscmp.slow_1200mv_0c.ddb
........\..\ZX_SOPC.tiscmp.slow_1200mv_85c.ddb
........\..\ZX_SOPC.tis_db_list.ddb
........\..\ZX_SOPC.tmw_info
........\DDS.bdf
........\DDS.v
........\EP4CE10F17C8N.tcl
........\epcs.v
........\epcs_boot_rom_synth.hex
........\FangROM.bsf
........\FangROM.mif

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