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DCT_verilog

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-12-25
  • Size : 496kb
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  • Author :荣****
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Introduction - If you have any usage issues, please Google them yourself
DCT is a digital image processing a basic algorithm to achieve the conversion the time domain to the frequency domain, and thus remove the domain relevance of data in favor of the quantized transform coefficients using run-length encoding and Huffman encoding.
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10.3
....\chart
....\.....\Thumbs.db
....\.....\图10-18.bmp
....\.....\图10-19.bmp
....\.....\图10-20.bmp
....\.....\图10-22.bmp
....\.....\图10-23.bmp
....\.....\图10-25.bmp
....\.....\图10-28.bmp
....\.....\表10-3.bmp
....\dct.cr.mti
....\dct.mpf
....\dct.v
....\dct_cos_table.v
....\dct_mac.v
....\dct_syn.v
....\dct_testbench.v
....\dctu.v
....\dctub.v
....\fdct.v
....\qnr.cr.mti
....\timescale.v
....\transcript
....\vsim.wlf
....\wave
....\....\Thumbs.db
....\....\dct.bmp
....\....\dct_testbench.bmp
....\....\dctu.bmp
....\....\dctub.bmp
....\....\fdct.bmp
....\....\zigzag.bmp
....\work
....\....\_info
....\....\bench_top
....\....\.........\_primary.dat
....\....\.........\_primary.vhd
....\....\.........\verilog.asm
....\....\dct
....\....\...\_primary.dat
....\....\...\_primary.vhd
....\....\...\verilog.asm
....\....\dct_mac
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\.......\verilog.asm
....\....\dct_syn
....\....\.......\_primary.dat
....\....\.......\_primary.vhd
....\....\.......\verilog.asm
....\....\dct_testbench
....\....\.............\_primary.dat
....\....\.............\_primary.vhd
....\....\.............\verilog.asm
....\....\dctu
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\....\verilog.asm
....\....\dctub
....\....\.....\_primary.dat
....\....\.....\_primary.vhd
....\....\.....\verilog.asm
....\....\fdct
....\....\....\_primary.dat
....\....\....\_primary.vhd
....\....\....\verilog.asm
....\....\zigzag
....\....\......\_primary.dat
....\....\......\_primary.vhd
....\....\......\verilog.asm
....\zigzag.v
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