vivado 下的可逆计数器项目，使用VERILOG语言编写，基于FPGA v

cnt10
.....\cnt10.cache
.....\...........\compile_simlib
.....\...........\wt
.....\...........\..\java_command_handlers.wdf
.....\...........\..\synthesis.wdf
.....\...........\..\synthesis_details.wdf
.....\...........\..\webtalk_pa.xml
.....\cnt10.hw
.....\........\hw_1
.....\........\....\hw.xml
.....\........\....\wave
.....\........\webtalk
.....\........\.......\.xsim_webtallk.info
.....\........\.......\labtool_webtalk.log
.....\........\.......\usage_statistics_ext_labtool.html
.....\........\.......\usage_statistics_ext_labtool.xml
.....\cnt10.runs
.....\..........\.jobs
.....\..........\.....\vrs_config_1.xml
.....\..........\.....\vrs_config_10.xml
.....\..........\.....\vrs_config_11.xml
.....\..........\.....\vrs_config_12.xml
.....\..........\.....\vrs_config_13.xml
.....\..........\.....\vrs_config_14.xml
.....\..........\.....\vrs_config_15.xml
.....\..........\.....\vrs_config_2.xml
.....\..........\.....\vrs_config_3.xml
.....\..........\.....\vrs_config_4.xml
.....\..........\.....\vrs_config_5.xml
.....\..........\.....\vrs_config_6.xml
.....\..........\.....\vrs_config_7.xml
.....\..........\.....\vrs_config_8.xml
.....\..........\.....\vrs_config_9.xml
.....\..........\impl_1
.....\..........\......\.Vivado_Implementation.queue.rst
.....\..........\......\.Xil
.....\..........\......\.init_design.begin.rst
.....\..........\......\.init_design.end.rst
.....\..........\......\.opt_design.begin.rst
.....\..........\......\.opt_design.end.rst
.....\..........\......\.place_design.begin.rst
.....\..........\......\.place_design.end.rst
.....\..........\......\.route_design.begin.rst
.....\..........\......\.route_design.end.rst
.....\..........\......\.vivado.begin.rst
.....\..........\......\.vivado.end.rst
.....\..........\......\.write_bitstream.begin.rst
.....\..........\......\.write_bitstream.end.rst
.....\..........\......\ISEWrap.js
.....\..........\......\ISEWrap.sh
.....\..........\......\gen_run.xml
.....\..........\......\htr.txt
.....\..........\......\init_design.pb
.....\..........\......\opt_design.pb
.....\..........\......\place_design.pb
.....\..........\......\project.wdf
.....\..........\......\route_design.pb
.....\..........\......\rundef.js
.....\..........\......\runme.bat
.....\..........\......\runme.log
.....\..........\......\runme.sh
.....\..........\......\top.bit
.....\..........\......\top.tcl
.....\..........\......\top.vdi
.....\..........\......\top_3884.backup.vdi
.....\..........\......\top_6048.backup.vdi
.....\..........\......\top_clock_utilization_placed.rpt
.....\..........\......\top_control_sets_placed.rpt
.....\..........\......\top_drc_opted.rpt
.....\..........\......\top_drc_routed.pb
.....\..........\......\top_drc_routed.rpt
.....\..........\......\top_io_placed.rpt
.....\..........\......\top_opt.dcp
.....\..........\......\top_placed.dcp
.....\..........\......\top_power_routed.rpt
.....\..........\......\top_power_summary_routed.pb
.....\..........\......\top_route_status.pb
.....\..........\......\top_route_status.rpt
.....\..........\......\top_routed.dcp
.....\..........\......\top_timing_summary_routed.rpt
.....\..........\......\top_timing_summary_routed.rpx
.....\..........\......\top_utilization_placed.pb
.....\..........\......\top_utilization_placed.rpt
.....\..........\......\usage_statistics_webtalk.html
.....\..........\......\usage_statistics_webtalk.xml
.....\..........\......\vivado.jou
.....\..........\......\vivado.pb
.....\..........\......\vivado_3884.backup.jou
.....\..........\......\vivado_4300.backup.jou
.....\..........\......\vivado_5900.backup.jou
.....\..........\......\vivado_6048.backup.jou
.....\..........\......\vivado_6508.backup.jou
.....\..........\......\write_bitstream.pb
.....\..........\synth_1
.....\..........\.......\.Vivado_Synthesis.queue.rst
.....\..........\.......\.Xil
.....\..........\.......\.vivado.begin.rst
.....\..........\.......\.vivado.end.rst
.....\..........\.......\ISEWrap.js

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