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DDDDDDDDDSSS

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-12-29
  • Size : 2.71mb
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  • Author :wang*****
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FPGA realization DDS sine, square, triangle wave generator Verilog program (verified) Quartus Project Files
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DDDDDDDDDSSS\.sopc_builder\filters.xml
............\altpll0.bsf
............\altpll0.inc
............\altpll0.ppf
............\altpll0.qip
............\altpll0.v
............\altpll0_bb.v
............\boxing.bsf
............\control.bsf
............\counter.bsf
............\db\add_sub_unc.tdf
............\..\add_sub_vnc.tdf
............\..\altpll_do32.tdf
............\..\altpll_hd42.tdf
............\..\altpll_hua2.tdf
............\..\altpll_jua2.tdf
............\..\altsyncram_96a1.tdf
............\..\altsyncram_ep91.tdf
............\..\altsyncram_h2a1.tdf
............\..\altsyncram_i7a1.tdf
............\..\altsyncram_nq91.tdf
............\..\altsyncram_q3a1.tdf
............\..\alt_u_div_16f.tdf
............\..\alt_u_div_36f.tdf
............\..\alt_u_div_39f.tdf
............\..\alt_u_div_59f.tdf
............\..\alt_u_div_69f.tdf
............\..\alt_u_div_f9f.tdf
............\..\alt_u_div_l8f.tdf
............\..\alt_u_div_n8f.tdf
............\..\alt_u_div_o8f.tdf
............\..\alt_u_div_p2f.tdf
............\..\alt_u_div_p8f.tdf
............\..\alt_u_div_r5f.tdf
............\..\alt_u_div_t5f.tdf
............\..\alt_u_div_t8f.tdf
............\..\alt_u_div_v8f.tdf
............\..\logic_util_heursitic.dat
............\..\lpm_divide_4jm.tdf
............\..\lpm_divide_5jm.tdf
............\..\lpm_divide_6gm.tdf
............\..\lpm_divide_6jm.tdf
............\..\lpm_divide_7jm.tdf
............\..\lpm_divide_8jm.tdf
............\..\lpm_divide_98m.tdf
............\..\lpm_divide_9jm.tdf
............\..\lpm_divide_bjm.tdf
............\..\lpm_divide_cjm.tdf
............\..\lpm_divide_djm.tdf
............\..\lpm_divide_hjm.tdf
............\..\lpm_divide_nhm.tdf
............\..\lpm_divide_ohm.tdf
............\..\lpm_divide_q9m.tdf
............\..\lpm_divide_qhm.tdf
............\..\lpm_divide_r9m.tdf
............\..\lpm_divide_rhm.tdf
............\..\mult_4et.tdf
............\..\mult_5et.tdf
............\..\mult_7et.tdf
............\..\mult_hft.tdf
............\..\mult_mft.tdf
............\..\mux_7qc.tdf
............\..\mux_cqc.tdf
............\..\mux_src.tdf
............\..\My_DDS.cbx.xml
............\..\My_DDS.cmp.rdb
............\..\My_DDS.db_info
............\..\My_DDS.eco.cdb
............\..\My_DDS.hif
............\..\My_DDS.map.qmsg
............\..\My_DDS.map_bb.hdb
............\..\My_DDS.sim_ori.vwf
............\..\My_DDS.sld_design_entry.sci
............\..\My_DDS.tis_db_list.ddb
............\..\prev_cmp_My_DDS.asm.qmsg
............\..\prev_cmp_My_DDS.fit.qmsg
............\..\prev_cmp_My_DDS.map.qmsg
............\..\prev_cmp_My_DDS.qmsg
............\..\prev_cmp_My_DDS.sim.qmsg
............\..\prev_cmp_My_DDS.sta.qmsg
............\..\sign_div_unsign_5nh.tdf
............\..\sign_div_unsign_6nh.tdf
............\..\sign_div_unsign_7kh.tdf
............\..\sign_div_unsign_7nh.tdf
............\..\sign_div_unsign_8nh.tdf
............\..\sign_div_unsign_9nh.tdf
............\..\sign_div_unsign_anh.tdf
............\..\sign_div_unsign_cnh.tdf
............\..\sign_div_unsign_dnh.tdf
............\..\sign_div_unsign_enh.tdf
............\..\sign_div_unsign_inh.tdf
............\..\sign_div_unsign_olh.tdf
............\..\sign_div_unsign_plh.tdf
............\..\sign_div_unsign_rlh.tdf
............\..\sign_div_unsign_slh.tdf
............\..\wed.wsf
............\DDS_hzh.bsf
............\DDS_hzh.v
............\DDS_hzh.v.bak
............\DE0_Pin.tcl
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