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Code-speed-adjustment-circuit

  • Category : VHDL-FPGA-Verilog
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  • Update : 2015-12-30
  • Size : 681kb
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  • Author :谢****
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Based on the synchronous digital multiplex system, namely the input data stream rate is the same. If the number of each branch, according to the code flow rate is not directly to pick up, because after the multiplex synthesis of digital signal flow, at the receiving end is unable to connect back to the original signal, so to make the selection in front of the multiplex synchronous digital rate, we can in the design of synchronous digital multiplex system System with a yard in front speed adjustment unit to adjust the selection of speed rate, synchronization and after yards after tapping speed adjust to restore to the original rate.
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Code speed adjustment circuit.doc
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