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ex4_seg7

  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-01-05
  • Size : 143kb
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  • Author :贺****
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Introduction - If you have any usage issues, please Google them yourself
7-segment (not counting the decimal point) is also very simple principle, it is nothing more than the seven light-emitting diodes. This seven light-emitting diodes have a common terminal, must be connected to GND (common cathode LED) or contact VCC (common anode LED). On the other end of the diode 7 is controlled accordingly will be able to control their light and dark. Different combinations of light and dark to produce a display of the numbers 0-9.
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ex4_seg7\sm4205的管脚图和led段码表.txt
........\verilogled7\db\led_seg7.db_info
........\...........\..\led_seg7.ipinfo
........\...........\..\led_seg7.sld_design_entry.sci
........\...........\..\prev_cmp_led_seg7.asm.qmsg
........\...........\..\prev_cmp_led_seg7.fit.qmsg
........\...........\..\prev_cmp_led_seg7.map.qmsg
........\...........\..\prev_cmp_led_seg7.qmsg
........\...........\..\prev_cmp_led_seg7.tan.qmsg
........\...........\incremental_db\compiled_partitions\led_seg7.db_info
........\...........\..............\...................\led_seg7.root_partition.map.kpt
........\...........\..............\README
........\...........\led_seg7.asm.rpt
........\...........\led_seg7.cdf
........\...........\led_seg7.done
........\...........\led_seg7.dpf
........\...........\led_seg7.fit.rpt
........\...........\led_seg7.fit.smsg
........\...........\led_seg7.fit.summary
........\...........\led_seg7.flow.rpt
........\...........\led_seg7.map.rpt
........\...........\led_seg7.map.summary
........\...........\led_seg7.pin
........\...........\led_seg7.pof
........\...........\led_seg7.qpf
........\...........\led_seg7.qsf
........\...........\led_seg7.qws
........\...........\led_seg7.tan.rpt
........\...........\led_seg7.tan.summary
........\...........\led_seg7.v
........\...........\led_seg7_assignment_defaults.qdf
........\数码管显示实验.pdf
........\verilogled7\incremental_db\compiled_partitions
........\...........\db
........\...........\incremental_db
........\...........\output_files
........\verilogled7
ex4_seg7
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