VGA controller based on NIOS, resolution and display area show the median, the memory depth can be adjusted, has been in Altera cyclone II under the condition of test through the end of the quartus13.0 development environment of the host with Avalon standard

vga_test\.qsys_edit\filters.xml
........\..........\preferences.xml
........\db\add_sub_8ri.tdf
........\..\altera_mult_add_mpt2.v
........\..\altera_mult_add_opt2.v
........\..\altsyncram_0bc1.tdf
........\..\altsyncram_0ff1.tdf
........\..\altsyncram_2q14.tdf
........\..\altsyncram_3q14.tdf
........\..\altsyncram_4bc1.tdf
........\..\altsyncram_4q14.tdf
........\..\altsyncram_5q14.tdf
........\..\altsyncram_6ec1.tdf
........\..\altsyncram_9tl1.tdf
........\..\altsyncram_9vc1.tdf
........\..\altsyncram_aeq1.tdf
........\..\altsyncram_beq1.tdf
........\..\altsyncram_ceq1.tdf
........\..\altsyncram_deq1.tdf
........\..\altsyncram_gef1.tdf
........\..\altsyncram_gp14.tdf
........\..\altsyncram_hk71.tdf
........\..\altsyncram_idg1.tdf
........\..\altsyncram_lmu.tdf
........\..\altsyncram_m3g1.tdf
........\..\altsyncram_mdg1.tdf
........\..\altsyncram_mlg1.tdf
........\..\altsyncram_mp14.tdf
........\..\altsyncram_n3g1.tdf
........\..\altsyncram_pmu.tdf
........\..\altsyncram_qed1.tdf
........\..\altsyncram_r1h1.tdf
........\..\altsyncram_rpu.tdf
........\..\altsyncram_udq1.tdf
........\..\alt_synch_pipe_iv7.tdf
........\..\alt_synch_pipe_jv7.tdf
........\..\alt_synch_pipe_kv7.tdf
........\..\alt_synch_pipe_lv7.tdf
........\..\alt_synch_pipe_mv7.tdf
........\..\alt_synch_pipe_nv7.tdf
........\..\a_dpfifo_8t21.tdf
........\..\a_fefifo_7cf.tdf
........\..\a_gray2bin_mdb.tdf
........\..\a_gray2bin_odb.tdf
........\..\a_graycounter_e2c.tdf
........\..\a_graycounter_f2c.tdf
........\..\a_graycounter_g2c.tdf
........\..\a_graycounter_h2c.tdf
........\..\a_graycounter_q96.tdf
........\..\a_graycounter_s96.tdf
........\..\cmpr_5cc.tdf
........\..\cmpr_736.tdf
........\..\cmpr_8cc.tdf
........\..\cmpr_936.tdf
........\..\cmpr_9cc.tdf
........\..\cmpr_acc.tdf
........\..\cntr_02j.tdf
........\..\cntr_0ci.tdf
........\..\cntr_1ci.tdf
........\..\cntr_2ci.tdf
........\..\cntr_3ci.tdf
........\..\cntr_4ci.tdf
........\..\cntr_fjb.tdf
........\..\cntr_gui.tdf
........\..\cntr_nbi.tdf
........\..\cntr_obi.tdf
........\..\cntr_rj7.tdf
........\..\cntr_sbi.tdf
........\..\cntr_v1j.tdf
........\..\dcfifo_1fi1.tdf
........\..\dcfifo_3fi1.tdf
........\..\dcfifo_4fi1.tdf
........\..\dcfifo_pei1.tdf
........\..\dcfifo_vhi1.tdf
........\..\decode_o37.tdf
........\..\decode_rqf.tdf
........\..\dffpipe_b09.tdf
........\..\dffpipe_c09.tdf
........\..\dffpipe_c2e.tdf
........\..\dffpipe_d09.tdf
........\..\dffpipe_e09.tdf
........\..\dffpipe_f09.tdf
........\..\dffpipe_g09.tdf
........\..\dffpipe_h09.tdf
........\..\dffpipe_i09.tdf
........\..\disp_fifo.vhd
........\..\dpram_5h21.tdf
........\..\ip\vga_test\submodules\altera_avalon_sc_fifo.v
........\..\..\........\..........\altera_avalon_st_pipeline_base.v
........\..\..\........\..........\altera_merlin_address_alignment.sv
........\..\..\........\..........\altera_merlin_arbitrator.sv
........\..\..\........\..........\altera_merlin_burst_adapter.sv
........\..\..\........\..........\altera_merlin_burst_uncompressor.sv
........\..\..\........\..........\altera_merlin_master_agent.sv
........\..\..\........\..........\altera_merlin_master_translator.sv
........\..\..\........\..........\altera_merlin_slave_agent.sv
........\..\..\........\..........\altera_merlin_slave_translator.sv
........\..\..\........\..........\altera_merlin_traffic_limiter.sv
........\..\..\........\..........\altera_merlin_width_adapter.sv
........\..\..\........\..........\altera_reset_controller.sdc

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