a small example of the realization of the love you state machine with Verilog

loveyou\design\loveyou.v
.......\......\loveyou.v.bak
.......\sim\run.do
.......\...\run.do.bak
.......\...\tb_loveyou.v
.......\...\tb_loveyou.v.bak
.......\...\virtuals.do
.......\...\vsim.wlf
.......\...\work\@_opt\vopt0rveds
.......\...\....\.....\vopt1vfe4s
.......\...\....\.....\vopt4thb7s
.......\...\....\.....\vopt5b5b4s
.......\...\....\.....\voptfi517s
.......\...\....\.....\voptie5vgs
.......\...\....\.....\voptj2vy6s
.......\...\....\.....\voptmytrgs
.......\...\....\.....\voptsegkgs
.......\...\....\.....\voptth4m7s
.......\...\....\.....\voptw76hds
.......\...\....\.....\voptx1th7s
.......\...\....\.....\voptymyk5r
.......\...\....\.....\_deps
.......\...\....\loveyou\_primary.dat
.......\...\....\.......\_primary.dbs
.......\...\....\.......\_primary.vhd
.......\...\....\tb_loveyou\_primary.dat
.......\...\....\..........\_primary.dbs
.......\...\....\..........\_primary.vhd
.......\...\....\_info
.......\...\....\.temp\vlog7h7i44
.......\...\....\.....\vlogh807zz
.......\...\....\.....\vlogm0c0ts
.......\...\....\.....\vlogvaci5k
.......\...\....\.....\vlogw0x23z
.......\...\....\.....\vlogyw7c01
.......\...\....\_vmake
.......\...\....\@_opt
.......\...\....\loveyou
.......\...\....\tb_loveyou
.......\...\....\_temp
.......\...\work
.......\design
.......\sim
loveyou

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