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anish-bit-masking

  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2016-01-23
  • Size : 205kb
  • Downloaded :0次
  • Author :gopalak*******
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
vhdl code for bit masking algorithm
Packet file list
(Preview for download)


anish bit masking\final.vhd
.................\final.vhd.bak
.................\modifiedfinal.vhd
.................\modifiedfinal.vhd.bak
.................\PROIMP\final_bit.cmd_log
.................\......\final_bit.lso
.................\......\final_bit.ngc
.................\......\final_bit.ngr
.................\......\final_bit.prj
.................\......\final_bit.stx
.................\......\final_bit.syr
.................\......\final_bit.xst
.................\......\final_bit_envsettings.html
.................\......\final_bit_modified.prj
.................\......\final_bit_modified_summary.html
.................\......\final_bit_modified_vhdl.prj
.................\......\final_bit_summary.html
.................\......\final_bit_vhdl.prj
.................\......\final_bit_xst.xrpt
.................\......\iseconfig\final_bit_modified.xreport
.................\......\.........\PROIMP.projectmgr
.................\......\iseconfig
.................\......\PROIMP.gise
.................\......\PROIMP.xise
.................\......\webtalk_pn.xml
.................\......\xst\dump.xst\final_bit.prj\ngx\notopt
.................\......\...\........\.............\...\opt
.................\......\...\........\.............\ngx
.................\......\...\........\final_bit.prj
.................\......\...\........\........._modified.prj\ngx\notopt
.................\......\...\........\......................\...\opt
.................\......\...\........\......................\ngx
.................\......\...\........\final_bit_modified.prj
.................\......\...\dump.xst
.................\......\...\projnav.tmp
.................\......\...\work\hdllib.ref
.................\......\...\....\hdpdeps.ref
.................\......\...\....\sub00\vhpl00.vho
.................\......\...\....\.....\vhpl01.vho
.................\......\...\....\.....\vhpl02.vho
.................\......\...\....\.....\vhpl03.vho
.................\......\...\....\sub00
.................\......\...\work
.................\......\xst
.................\......\_xmsgs\pn_parser.xmsgs
.................\......\......\xst.xmsgs
.................\......\_xmsgs
.................\PROIMP
.................\transcript
.................\vsim.wlf
.................\work\final_bit\design.dat
.................\....\.........\_primary.dat
.................\....\final_bit
.................\....\........._modified\design.dat
.................\....\..................\_primary.dat
.................\....\final_bit_modified
.................\....\_info
.................\....\.opt\work_final_bit_design.asm
.................\....\....\work__info
.................\....\....\_deps
.................\....\....\__model_tech_.._ieee__info
.................\....\....\__model_tech_.._std__info
.................\....\_opt
.................\....\....1\work_final_bit_modified_design.asm
.................\....\.....\work__info
.................\....\.....\_deps
.................\....\.....\__model_tech_.._ieee__info
.................\....\.....\__model_tech_.._std__info
.................\....\_opt1
.................\....\_temp
.................\work
anish bit masking
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