Use the Quartus II 9.1 to complete the tetris game, as long as you use a VGA and keyboard interface implementation of FPGA development board. The operation is simple, the use of VHDL and the Verilog language

eluosi_game\11.c
...........\altera_vhdl_support.vhd
...........\boot_rom.hex
...........\boot_rom.vhd
...........\button_isr_test.c
...........\button_pio.vhd
...........\Chain1.cdf
...........\cmp_state.ini
...........\component_builder_logfile.txt
...........\cpu.ocp
...........\cpu.vhd
...........\cpu_jtag_debug_module.vhd
...........\cpu_jtag_debug_module_wrapper.vhd
...........\cpu_ociram_default_contents.mif
...........\cpu_test_bench.vhd
...........\db\add_sub_ovb.tdf
...........\..\altsyncram_1kc1.tdf
...........\..\altsyncram_bhc1.tdf
...........\..\altsyncram_dno1.tdf
...........\..\altsyncram_gpm1.tdf
...........\..\altsyncram_u301.tdf
...........\..\altsyncram_vkt1.tdf
...........\..\alt_synch_pipe_bb3.tdf
...........\..\alt_synch_pipe_cb3.tdf
...........\..\alt_synch_pipe_db3.tdf
...........\..\a_dpfifo_83p.tdf
...........\..\a_fefifo_46d.tdf
...........\..\a_fefifo_7cf.tdf
...........\..\a_fefifo_v5d.tdf
...........\..\a_gray2bin_26b.tdf
...........\..\a_graycounter_626.tdf
...........\..\a_graycounter_726.tdf
...........\..\cntr_9c7.tdf
...........\..\cntr_df8.tdf
...........\..\cntr_i08.tdf
...........\..\cntr_rd8.tdf
...........\..\dcfifo_do01.tdf
...........\..\decode_9ie.tdf
...........\..\decode_imb.tdf
...........\..\decode_tkb.tdf
...........\..\dffpipe_9b3.tdf
...........\..\dffpipe_bb3.tdf
...........\..\dffpipe_cb3.tdf
...........\..\dffpipe_db3.tdf
...........\..\dpram_75p.tdf
...........\..\dpram_jor.tdf
...........\..\elsfk.db_info
...........\..\elsfk.eco.cdb
...........\..\elsfk.sld_design_entry.sci
...........\..\elsfk_cmp.qrpt
...........\..\mux_hic.tdf
...........\..\mux_sgc.tdf
...........\..\scfifo_1to.tdf
...........\delay_reset.bdf
...........\delay_reset.bsf
...........\delay_reset.vhd
...........\dma.vhd
...........\elsfk.asm.rpt
...........\elsfk.bdf
...........\elsfk.cdf
...........\elsfk.done
...........\elsfk.fit.eqn
...........\elsfk.fit.rpt
...........\elsfk.fit.summary
...........\elsfk.flow.rpt
...........\elsfk.map.eqn
...........\elsfk.map.rpt
...........\elsfk.map.summary
...........\elsfk.pin
...........\elsfk.pof
...........\elsfk.qpf
...........\elsfk.qsf
...........\elsfk.qsf.bak
...........\elsfk.qws
...........\elsfk.sof
...........\elsfk.tan.rpt
...........\elsfk.tan.summary
...........\elsfk_assignment_defaults.qdf
...........\FK.c
...........\FK.h
...........\FK1.c
...........\For_UP3.csv
...........\jtag_uart.vhd
...........\lcd.vhd
...........\led_pio.vhd
...........\lpm_counter1.bsf
...........\lpm_counter1.vhd
...........\lpm_counter1_wave0.jpg
...........\lpm_counter1_waveforms.html
...........\Multiplexer_3_Channel_M.v
...........\nios32.bsf
...........\nios32.ptf
...........\nios32.ptf.bak
...........\nios32.v
...........\nios32.vhd
...........\nios32_generation_script
...........\nios32_log.txt
...........\nios32_setup_quartus.tcl
...........\........im\atail-f.pl
...........\..........\dummy_file

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