This a verilog code for a kind of traffic light controller. The code was simulated and verificated on FPGA. When the code works on FPGA, it can be communicated with PC using serial debugging assistant. The PC can set the mode for traffic light controller: two-phase mode or four-phase mode. In the code, the serial interface is UART.

traffic_controller
..................\accum.v
..................\addr_decode.v
..................\adr.v
..................\alu.v
..................\clk_gen.v
..................\counter.v
..................\cpu.v
..................\cputop.v
..................\datact1.v
..................\machine.v
..................\machinect1.v
..................\ram.v
..................\register.v
..................\rom.v

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