FPGA-based VGA display dynamic, with patterns, checkerboard, and the image is displayed. And music playback. Using verilog language

bishe_VGA\core\Char_rom.qip
.........\....\Char_rom.v
.........\....\Char_rom_bb.v
.........\....\tupian.qip
.........\....\tupian.v
.........\....\tupian1.qip
.........\....\tupian1.v
.........\....\tupian1_bb.v
.........\....\tupian5.qip
.........\....\tupian5.v
.........\....\tupian5_bb.v
.........\....\tupian6.qip
.........\....\tupian6.v
.........\....\tupian6_bb.v
.........\....\tupian7.qip
.........\....\tupian7.v
.........\....\tupian7_bb.v
.........\....\tupian_bb.v
.........\....\vga_pll.ppf
.........\....\vga_pll.qip
.........\....\vga_pll.v
.........\....\vga_pll_bb.v
.........\dev\db\.cmp.kpt
.........\...\..\add_sub_7pc.tdf
.........\...\..\add_sub_8pc.tdf
.........\...\..\altsyncram_04a1.tdf
.........\...\..\altsyncram_28a1.tdf
.........\...\..\altsyncram_34a1.tdf
.........\...\..\altsyncram_58a1.tdf
.........\...\..\altsyncram_88a1.tdf
.........\...\..\altsyncram_b8a1.tdf
.........\...\..\altsyncram_e3a1.tdf
.........\...\..\altsyncram_h3a1.tdf
.........\...\..\altsyncram_k3a1.tdf
.........\...\..\altsyncram_n3a1.tdf
.........\...\..\altsyncram_ooa1.tdf
.........\...\..\altsyncram_p7a1.tdf
.........\...\..\altsyncram_q3a1.tdf
.........\...\..\altsyncram_s7a1.tdf
.........\...\..\altsyncram_t3a1.tdf
.........\...\..\altsyncram_t401.tdf
.........\...\..\altsyncram_v7a1.tdf
.........\...\..\alt_u_div_87f.tdf
.........\...\..\lpm_divide_5bm.tdf
.........\...\..\mult_oct.tdf
.........\...\..\prev_cmp_vga_donghua.qmsg
.........\...\..\sign_div_unsign_qlh.tdf
.........\...\..\vga_donghua.db_info
.........\...\..\vga_donghua.sld_design_entry.sci
.........\...\..\vga_pll_altpll.v
.........\...\..\vga_pll_altpll1.v
.........\...\..\vga_pll_altpll2.v
.........\...\greybox_tmp\cbx_args.txt
.........\...\incremental_db\compiled_partitions\vga_donghua.db_info
.........\...\..............\README
.........\...\output_files\greybox_tmp\cbx_args.txt
.........\...\............\output_file.jic
.........\...\............\output_file.map
.........\...\............\vga_donghua.asm.rpt
.........\...\............\vga_donghua.done
.........\...\............\vga_donghua.eda.rpt
.........\...\............\vga_donghua.fit.rpt
.........\...\............\vga_donghua.fit.smsg
.........\...\............\vga_donghua.fit.summary
.........\...\............\vga_donghua.flow.rpt
.........\...\............\vga_donghua.jdi
.........\...\............\vga_donghua.map.rpt
.........\...\............\vga_donghua.map.smsg
.........\...\............\vga_donghua.map.summary
.........\...\............\vga_donghua.pin
.........\...\............\vga_donghua.sof
.........\...\............\vga_donghua.sta.rpt
.........\...\............\vga_donghua.sta.summary
.........\...\PLLJ_PLLSPE_INFO.txt
.........\...\simulation\modelsim\vga_donghua.sft
.........\...\..........\........\vga_donghua.vo
.........\...\..........\........\vga_donghua_8_1200mv_0c_slow.vo
.........\...\..........\........\vga_donghua_8_1200mv_0c_v_slow.sdo
.........\...\..........\........\vga_donghua_8_1200mv_85c_slow.vo
.........\...\..........\........\vga_donghua_8_1200mv_85c_v_slow.sdo
.........\...\..........\........\vga_donghua_min_1200mv_0c_fast.vo
.........\...\..........\........\vga_donghua_min_1200mv_0c_v_fast.sdo
.........\...\..........\........\vga_donghua_modelsim.xrf
.........\...\..........\........\vga_donghua_v.sdo
.........\...\tupian2.qip
.........\...\tupian2.v
.........\...\tupian2_bb.v
.........\...\tupian3.qip
.........\...\tupian3.v
.........\...\tupian3_bb.v
.........\...\tupian4.qip
.........\...\tupian4.v
.........\...\tupian4_bb.v
.........\...\vga_donghua.qpf
.........\...\vga_donghua.qsf
.........\...\vga_donghua.qws
.........\image\111.bmp
.........\.....\222.bmp
.........\.....\333.bmp
.........\.....\444.bmp

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