Use Verilog implementation of asynchronous fifo functionality

fifo\altera_mf.v
....\fifo.v
....\fifo_test.cr.mti
....\fifo_test.mpf
....\fifo_test.v
....\ram256X16.v
....\rom256x16.txt
....\vsim.wlf
....\wave.do
....\.ork\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s\verilog.asm
....\....\..........................................\_primary.dat
....\....\..........................................\_primary.vhd
....\....\..............m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n\_primary.dat
....\....\...............................................\_primary.vhd
....\....\...................m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n\verilog.asm
....\....\...........................................................\_primary.dat
....\....\...........................................................\_primary.vhd
....\....\.m@f_cycloneiiigl_m_cntr\_primary.dat
....\....\........................\_primary.vhd
....\....\..................n_cntr\_primary.dat
....\....\........................\_primary.vhd
....\....\..................pll\_primary.dat
....\....\.....................\_primary.vhd
....\....\..................scale_cntr\_primary.dat
....\....\............................\_primary.vhd
....\....\..............._pll\_primary.dat
....\....\...................\_primary.vhd
....\....\.....pll_reg\_primary.dat
....\....\............\_primary.vhd
....\....\.....stratixiii_pll\_primary.dat
....\....\...................\_primary.vhd
....\....\.............._pll\_primary.dat
....\....\..................\_primary.vhd
....\....\............_pll\_primary.dat
....\....\................\_primary.vhd
....\....\alt3pram\_primary.dat
....\....\........\_primary.vhd
....\....\...accumulate\_primary.dat
....\....\.............\_primary.vhd
....\....\...clklock\_primary.dat
....\....\..........\_primary.vhd
....\....\...ddio_bidir\_primary.dat
....\....\.............\_primary.vhd
....\....\........in\_primary.dat
....\....\..........\_primary.vhd
....\....\........out\_primary.dat
....\....\...........\_primary.vhd
....\....\....pram\_primary.dat
....\....\........\_primary.vhd
....\....\...era_std_synchronizer\_primary.dat
....\....\.......................\_primary.vhd
....\....\......................._bundle\_primary.dat
....\....\..............................\_primary.vhd
....\....\...fp_mult\_primary.dat
....\....\..........\_primary.vhd
....\....\...lvds_rx\_primary.dat
....\....\..........\_primary.vhd
....\....\........tx\_primary.dat
....\....\..........\_primary.vhd
....\....\...mult_accum\_primary.dat
....\....\.............\_primary.vhd
....\....\.........dd\_primary.dat
....\....\...........\_primary.vhd
....\....\...parallel_flash_loader\_primary.dat
....\....\........................\_primary.vhd
....\....\....ll\_primary.dat
....\....\......\_primary.vhd
....\....\...serial_flash_loader\_primary.dat
....\....\......................\_primary.vhd
....\....\....hift_taps\_primary.dat
....\....\.............\_primary.vhd
....\....\....ource_probe\_primary.dat
....\....\...............\_primary.vhd
....\....\....qrt\_primary.dat
....\....\.......\_primary.vhd
....\....\.....uare\_primary.dat
....\....\.........\_primary.vhd
....\....\....tratixii_oct\_primary.dat
....\....\................\_primary.vhd
....\....\....yncram\verilog.asm
....\....\..........\_primary.dat
....\....\..........\_primary.vhd
....\....\..._aeq_s4\_primary.dat
....\....\..........\_primary.vhd
....\....\....cal\_primary.dat
....\....\.......\_primary.vhd
....\....\......._c3gxb\_primary.dat
....\....\.............\_primary.vhd
....\....\........mm\_primary.dat
....\....\..........\_primary.vhd
....\....\........sv\_primary.dat
....\....\..........\_primary.vhd
....\....\....dfe\_primary.dat
....\....\.......\_primary.vhd
....\....\....eyemon\_primary.dat
....\....\..........\_primary.vhd
....\....\.rm_m_cntr\_primary.dat
....\....\..........\_primary.vhd
....\....\....n_cntr\_primary.dat
....\....\..........\_primary.vhd

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