EP1C3-uart 1 verilog, implements a program to send and receive a 10 bit (that is, no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Baud-law decided by div_par parameters defined in the program, you can change the parameters to achieve the appropriate baud rate. Value of the program is currently set div_par Is 0x145, the corresponding baud rate is 9600. An 8 times the baud rate clock to send or receive every bit of the time period is divided into eight time slots so that the pass Letter synchronization.

demo7-uart_1_verilog\db\prev_cmp_serial_1.asm.qmsg
....................\..\prev_cmp_serial_1.fit.qmsg
....................\..\prev_cmp_serial_1.map.qmsg
....................\..\prev_cmp_serial_1.qmsg
....................\..\prev_cmp_serial_1.tan.qmsg
....................\..\serial_1.asm.qmsg
....................\..\serial_1.cbx.xml
....................\..\serial_1.cmp.ecobp
....................\..\serial_1.cmp.kpt
....................\..\serial_1.cmp.rdb
....................\..\serial_1.cmp0.ddb
....................\..\serial_1.cmp_merge.kpt
....................\..\serial_1.db_info
....................\..\serial_1.eco.cdb
....................\..\serial_1.fit.qmsg
....................\..\serial_1.hier_info
....................\..\serial_1.hif
....................\..\serial_1.lpc.html
....................\..\serial_1.lpc.rdb
....................\..\serial_1.lpc.txt
....................\..\serial_1.map.bpm
....................\..\serial_1.map.cdb
....................\..\serial_1.map.ecobp
....................\..\serial_1.map.hdb
....................\..\serial_1.map.kpt
....................\..\serial_1.map.logdb
....................\..\serial_1.map.qmsg
....................\..\serial_1.map_bb.cdb
....................\..\serial_1.map_bb.hdb
....................\..\serial_1.map_bb.logdb
....................\..\serial_1.pre_map.cdb
....................\..\serial_1.pre_map.hdb
....................\..\serial_1.rtlv.hdb
....................\..\serial_1.rtlv_sg.cdb
....................\..\serial_1.rtlv_sg_swap.cdb
....................\..\serial_1.sgdiff.cdb
....................\..\serial_1.sgdiff.hdb
....................\..\serial_1.sld_design_entry.sci
....................\..\serial_1.sld_design_entry_dsc.sci
....................\..\serial_1.syn_hier_info
....................\..\serial_1.tan.qmsg
....................\..\serial_1.tis_db_list.ddb
....................\..\serial_1.tmw_info
....................\incremental_db\compiled_partitions\serial_1.root_partition.cmp.atm
....................\..............\...................\serial_1.root_partition.cmp.dfp
....................\..............\...................\serial_1.root_partition.cmp.hdbx
....................\..............\...................\serial_1.root_partition.cmp.kpt
....................\..............\...................\serial_1.root_partition.cmp.logdb
....................\..............\...................\serial_1.root_partition.cmp.rcf
....................\..............\...................\serial_1.root_partition.map.atm
....................\..............\...................\serial_1.root_partition.map.dpi
....................\..............\...................\serial_1.root_partition.map.hdbx
....................\..............\...................\serial_1.root_partition.map.kpt
....................\..............\README
....................\serial_1.asm.rpt
....................\serial_1.done
....................\serial_1.dpf
....................\serial_1.fit.rpt
....................\serial_1.fit.smsg
....................\serial_1.fit.summary
....................\serial_1.flow.rpt
....................\serial_1.map.rpt
....................\serial_1.map.summary
....................\serial_1.pin
....................\serial_1.pof
....................\serial_1.qpf
....................\serial_1.qsf
....................\serial_1.qws
....................\serial_1.sof
....................\serial_1.tan.rpt
....................\serial_1.tan.summary
....................\serial_1.v
....................\incremental_db\compiled_partitions
....................\db
....................\incremental_db
demo7-uart_1_verilog

• We are an exchange download platform that only provides communication channels. The downloaded content comes from the internet. Except for download issues, please Google on your own.
• The downloaded content is provided for members to upload. If it unintentionally infringes on your copyright, please contact us.
• Please use Winrar for decompression tools
• If download fail, Try it againg or Feedback to us.
• If downloaded content did not match the introduction, Feedback to us，Confirm and will be refund.
• Before downloading, you can inquire through the uploaded person information

Nothing．