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  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-03-13
  • Size : 2.97mb
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  • Author :曾***
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Introduction - If you have any usage issues, please Google them yourself
FPGA VGA
Packet file list
(Preview for download)


vga_dis
.......\20141126.cfi
.......\20141126.mcs
.......\20141126.prm
.......\20141126.sig
.......\20141230.cfi
.......\20141230.mcs
.......\20141230.prm
.......\_ngo
.......\....\cs_icon_pro
.......\....\...........\_xmsgs
.......\....\...........\......\xst.xmsgs
.......\....\...........\coregen.cgc
.......\....\...........\coregen.cgp
.......\....\...........\coregen.log
.......\....\...........\generate_icon_pro.xco
.......\....\...........\icon_pro.gise
.......\....\...........\icon_pro.vhd
.......\....\...........\icon_pro.vho
.......\....\...........\icon_pro.xco
.......\....\...........\icon_pro.xise
.......\....\...........\icon_pro_flist.txt
.......\....\...........\icon_pro_readme.txt
.......\....\...........\icon_pro_xmdf.tcl
.......\....\...........\tmp
.......\....\...........\...\_cg
.......\....\...........\...\_xmsgs
.......\....\...........\...\......\pn_parser.xmsgs
.......\....\cs_ila_pro_0
.......\....\............\_xmsgs
.......\....\............\......\xst.xmsgs
.......\....\............\coregen.cgc
.......\....\............\coregen.cgp
.......\....\............\coregen.log
.......\....\............\generate_ila_pro_0.xco
.......\....\............\ila_pro_0.cdc
.......\....\............\ila_pro_0.gise
.......\....\............\ila_pro_0.vhd
.......\....\............\ila_pro_0.vho
.......\....\............\ila_pro_0.xco
.......\....\............\ila_pro_0.xise
.......\....\............\ila_pro_0_flist.txt
.......\....\............\ila_pro_0_readme.txt
.......\....\............\ila_pro_0_xmdf.tcl
.......\....\............\tmp
.......\....\............\...\_cg
.......\....\............\...\_xmsgs
.......\....\............\...\......\pn_parser.xmsgs
.......\....\icon_pro.ngc
.......\....\ila_pro_0.ngc
.......\....\netlist.lst
.......\....\vga_dis_cs_signalbrowser.ngo
.......\....\vga_dis_cs_signalbrowser.ver
.......\_xmsgs
.......\......\bitgen.xmsgs
.......\......\map.xmsgs
.......\......\netgen.xmsgs
.......\......\ngcbuild.xmsgs
.......\......\ngdbuild.xmsgs
.......\......\par.xmsgs
.......\......\pn_parser.xmsgs
.......\......\trce.xmsgs
.......\......\xst.xmsgs
.......\ipcore_dir
.......\..........\_xmsgs
.......\..........\......\cg.xmsgs
.......\..........\......\pn_parser.xmsgs
.......\..........\coregen.cgp
.......\..........\coregen.log
.......\..........\create_my_dcm.tcl
.......\..........\create_rom.tcl
.......\..........\edit_my_dcm.tcl
.......\..........\my_dcm
.......\..........\......\clk_wiz_v3_2_readme.txt
.......\..........\......\doc
.......\..........\......\...\clk_wiz_ds709.pdf
.......\..........\......\...\clk_wiz_gsg521.pdf
.......\..........\......\...\clk_wiz_v3_2_readme.txt
.......\..........\......\...\clk_wiz_v3_2_vinfo.html
.......\..........\......\example_design
.......\..........\......\..............\my_dcm_exdes.v
.......\..........\......\generate
.......\..........\......\........\clk_wiz_v3_2_generate.tcl
.......\..........\......\........\clk_wiz_v3_2_model.tcl
.......\..........\......\........\run_legacy_tcl_flow.tcl
.......\..........\......\implement
.......\..........\......\.........\implement.bat
.......\..........\......\.........\implement.sh
.......\..........\......\.........\planAhead_ise.bat
.......\..........\......\.........\planAhead_ise.sh
.......\..........\......\.........\planAhead_ise.tcl
.......\..........\......\.........\planAhead_rdn.bat
.......\..........\......\.........\planAhead_rdn.sh
.......\..........\......\.........\planAhead_rdn.tcl
.......\..........\......\.........\xst.prj
.......\..........\......\.........\xst.scr
.......\..........\......\my_dcm.ucf
.......\..........\......\my_dcm.xdc
.......\..........\......\simulation
.......\..........\......\..........\functional
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