This is a two-dimensional lift-style 9/7 discrete wavelet of Verilog source code, this is Encoder

Packet : 10721576597_2d_2level.rar filelist
97_2D_2Level
97_2D_2Level\Add.v
97_2D_2Level\bidirec.v
97_2D_2Level\Chang3to2.v
97_2D_2Level\cmp_state.ini
97_2D_2Level\coff_a.v
97_2D_2Level\coff_b.v
97_2D_2Level\coff_l.v
97_2D_2Level\coff_r.v
97_2D_2Level\ControlPath.v
97_2D_2Level\counter_128bits.v
97_2D_2Level\Counter_State.v
97_2D_2Level\DataPath.v
97_2D_2Level\db
97_2D_2Level\db\Add.verilogview
97_2D_2Level\db\bidirec.verilogview
97_2D_2Level\db\Chang3to2.verilogview
97_2D_2Level\db\coff_a.verilogview
97_2D_2Level\db\coff_b.verilogview
97_2D_2Level\db\coff_l.verilogview
97_2D_2Level\db\coff_r.verilogview
97_2D_2Level\db\ControlPath.verilogview
97_2D_2Level\db\Counter_128bits.verilogview
97_2D_2Level\db\Counter_State.verilogview
97_2D_2Level\db\DataPath.verilogview
97_2D_2Level\db\FDWT97_Address_R.verilogview
97_2D_2Level\db\FDWT97_Control.verilogview
97_2D_2Level\db\FDWT97_DataPath.verilogview
97_2D_2Level\db\FDWT97_TOP.verilogview
97_2D_2Level\db\FDWT_ALL-sim.vwf
97_2D_2Level\db\FDWT_ALL.csf.msg
97_2D_2Level\db\FDWT_ALL.db_info
97_2D_2Level\db\FDWT_ALL.FDWT_ALL.chip.tdb_netlist.EP20K400EBC652-1X.csf.tdb
97_2D_2Level\db\FDWT_ALL.FDWT_ALL.chip.tim_manager.EP20K400EBC652-1X.csf.ddb
97_2D_2Level\db\FDWT_ALL.FDWT_ALL.csf.hdb
97_2D_2Level\db\FDWT_ALL.FDWT_ALL.csf.rdb
97_2D_2Level\db\FDWT_ALL.FDWT_ALL.db_entries.csf.cdb
97_2D_2Level\db\FDWT_ALL.FDWT_ALL.sgate_entries.csf.cdb
97_2D_2Level\db\FDWT_ALL.FDWT_ALL.ssf.hdb
97_2D_2Level\db\FDWT_ALL.FDWT_ALL.ssf.rdb
97_2D_2Level\db\FDWT_ALL.psf.hdb
97_2D_2Level\db\FDWT_ALL.ssf.msg
97_2D_2Level\db\FDWT_ALL.verilogview
97_2D_2Level\db\IDWT97_Address_R.verilogview
97_2D_2Level\db\IDWT97_Control.verilogview
97_2D_2Level\db\IDWT97_DataPath.verilogview
97_2D_2Level\db\IDWT97_TOP.verilogview
97_2D_2Level\db\memory.verilogview
97_2D_2Level\db\PcToFPGA.verilogview
97_2D_2Level\db\Register_F.verilogview
97_2D_2Level\db\Register_I.verilogview
97_2D_2Level\db\sel_level.verilogview
97_2D_2Level\db\sld_design_entry.ice
97_2D_2Level\Debug.fsf
97_2D_2Level\FDWT97_Address_R.v
97_2D_2Level\FDWT97_Control.v
97_2D_2Level\FDWT97_DataPath.v
97_2D_2Level\FDWT97_TOP.v
97_2D_2Level\FDWT_ALL.csf
97_2D_2Level\FDWT_ALL.csf.rpt
97_2D_2Level\FDWT_ALL.eqn
97_2D_2Level\FDWT_ALL.pin
97_2D_2Level\FDWT_ALL.pof
97_2D_2Level\FDWT_ALL.psf
97_2D_2Level\FDWT_ALL.quartus
97_2D_2Level\FDWT_ALL.qws
97_2D_2Level\FDWT_ALL.sof
97_2D_2Level\FDWT_ALL.ssf
97_2D_2Level\FDWT_ALL.ssf.rpt
97_2D_2Level\FDWT_ALL.v
97_2D_2Level\FDWT_ALL.vwf
97_2D_2Level\FDWT_ALL_1.pof
97_2D_2Level\FDWT_ALL_2.pof
97_2D_2Level\IDWT97_Address_R.v
97_2D_2Level\IDWT97_Control.v
97_2D_2Level\IDWT97_DataPath.v
97_2D_2Level\IDWT97_TOP.v
97_2D_2Level\memory.v
97_2D_2Level\memory_bb.v
97_2D_2Level\memory_inst.v
97_2D_2Level\PctoFPGA.v
97_2D_2Level\Register_F.v
97_2D_2Level\Register_I.v
97_2D_2Level\Release.fsf
97_2D_2Level\sel_level.v
97_2D_2Level\serv_req_info.txt

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