It is a bridge between CPU and sensors where user can not connect sensors directly on CPU. It consumes very small number od LUTs and it is suitable for CPLD design. it works on following way, when logic detects falling edge of RX, then this action triggers other logic and then starts sending data on TX line

BR_GENERATOR.vhd
clkAdder.vhd
edgeDetector.vhd
HalfAdder.vhd
logicPkg.vhd
TX_modul.vhd

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