Learning for learning VHDL divider helps a lot of very good inside information

T2_DIV\cmp_state.ini
......\counter.bsf
......\counter.v
......\counter_bb.v
......\counter_wave0.jpg
......\counter_waveforms.html
......\db\cntr_adh.tdf
......\..\cntr_gs6.tdf
......\..\div.asm.qmsg
......\..\div.cbx.xml
......\..\div.cmp.cdb
......\..\div.cmp.hdb
......\..\div.cmp.logdb
......\..\div.cmp.rdb
......\..\div.cmp.tdb
......\..\div.cmp0.ddb
......\..\div.dbp
......\..\div.db_info
......\..\div.eco.cdb
......\..\div.eds_overflow
......\..\div.fit.qmsg
......\..\div.fnsim.hdb
......\..\div.fnsim.qmsg
......\..\div.hier_info
......\..\div.hif
......\..\div.map.cdb
......\..\div.map.hdb
......\..\div.map.logdb
......\..\div.map.qmsg
......\..\div.pre_map.cdb
......\..\div.pre_map.hdb
......\..\div.psp
......\..\div.pss
......\..\div.rtlv.hdb
......\..\div.rtlv_sg.cdb
......\..\div.rtlv_sg_swap.cdb
......\..\div.sgdiff.cdb
......\..\div.sgdiff.hdb
......\..\div.signalprobe.cdb
......\..\div.sim.hdb
......\..\div.sim.qmsg
......\..\div.sim.rdb
......\..\div.simfam
......\..\div.sim_ori.vwf
......\..\div.sld_design_entry.sci
......\..\div.sld_design_entry_dsc.sci
......\..\div.syn_hier_info
......\..\div.tan.qmsg
......\..\div.tis_db_list.ddb
......\..\div_cmp.qrpt
......\..\prev_cmp_div.asm.qmsg
......\..\prev_cmp_div.fit.qmsg
......\..\prev_cmp_div.map.qmsg
......\..\prev_cmp_div.qmsg
......\..\prev_cmp_div.sim.qmsg
......\..\prev_cmp_div.tan.qmsg
......\..\wed.wsf
......\div.asm.rpt
......\div.bdf
......\div.done
......\div.fit.rpt
......\div.fit.smsg
......\div.fit.summary
......\div.flow.rpt
......\div.map.eqn
......\div.map.rpt
......\div.map.summary
......\div.pin
......\div.pof
......\div.qpf
......\div.qsf
......\div.qws
......\div.sim.rpt
......\div.sof
......\div.tan.rpt
......\div.tan.summary
......\div.vwf
......\div_assignment_defaults.qdf
......\db
T2_DIV

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