FPGA SPI Verilog

FPGA实现SPI接口(包括主机和从机程序)\fpga实现spi接口\BUS_S.bsf
...................................\...............\BUS_S.inc
...................................\...............\BUS_S.v
...................................\...............\BUS_S_bb.v
...................................\...............\counter25.bsf
...................................\...............\counter25.inc
...................................\...............\counter25.v
...................................\...............\counter25_bb.v
...................................\...............\db\add_sub_3rh.tdf
...................................\...............\..\add_sub_5rh.tdf
...................................\...............\..\add_sub_6rh.tdf
...................................\...............\..\add_sub_7rh.tdf
...................................\...............\..\altsyncram_jam1.tdf
...................................\...............\..\cntr_dth.tdf
...................................\...............\..\decode_6lf.tdf
...................................\...............\..\mux_7hc.tdf
...................................\...............\..\mux_afc.tdf
...................................\...............\..\mux_lrd.tdf
...................................\...............\..\TEST.db_info
...................................\...............\..\TEST.ipinfo
...................................\...............\..\TEST.sim.vwf
...................................\...............\..\TEST.sld_design_entry.sci
...................................\...............\..\wed.wsf
...................................\...............\..\wed.zsf
...................................\...............\FIFO7.bsf
...................................\...............\FIFO7.inc
...................................\...............\FIFO7.v
...................................\...............\FIFO7_bb.v
...................................\...............\FIFO7_wave0.jpg
...................................\...............\FIFO7_waveforms.html
...................................\...............\FIFOSEL.bsf
...................................\...............\FIFOSEL.v
...................................\...............\FIFOSEL_RD.bsf
...................................\...............\FIFOSEL_RD.v
...................................\...............\INTERFACE.bdf
...................................\...............\INTERFACE.bsf
...................................\...............\LEDRun.bsf
...................................\...............\LEDRun.v
...................................\...............\MUX7.bsf
...................................\...............\MUX7.inc
...................................\...............\MUX7.v
...................................\...............\MUX7_bb.v
...................................\...............\RAM7.bsf
...................................\...............\RAM7.inc
...................................\...............\RAM7.v
...................................\...............\RAM7_bb.v
...................................\...............\RAM_RD.bsf
...................................\...............\RAM_RD.v
...................................\...............\RAM_TEST.bsf
...................................\...............\RAM_TEST.inc
...................................\...............\RAM_TEST.v
...................................\...............\RAM_TEST_bb.v
...................................\...............\RAM_WR.bsf
...................................\...............\RAM_WR.v
...................................\...............\SPI.bdf
...................................\...............\SPI.bsf
...................................\...............\spiprocess.bsf
...................................\...............\spiprocess.v
...................................\...............\TEST.asm.rpt
...................................\...............\TEST.bdf
...................................\...............\TEST.cdf
...................................\...............\TEST.done
...................................\...............\TEST.fit.rpt
.............

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