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Location : Home Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
  • Category : VHDL-FPGA-Verilog
  • Tags :
  • Update : 2016-04-07
  • Size : 381kb
  • Downloaded :0次
  • Author :万***
  • About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Multi-function digital clock verilog procedures, can be used for date time and display.
Packet file list
(Preview for download)


clock\clock.v
.....\cmp_state.ini
.....\count8.v
.....\db\add_sub_0ih.tdf
.....\..\shuzizhong.asm.qmsg
.....\..\shuzizhong.cbx.xml
.....\..\shuzizhong.cmp.cdb
.....\..\shuzizhong.cmp.hdb
.....\..\shuzizhong.cmp.rdb
.....\..\shuzizhong.cmp.tdb
.....\..\shuzizhong.cmp0.ddb
.....\..\shuzizhong.db_info
.....\..\shuzizhong.eco.cdb
.....\..\shuzizhong.fit.qmsg
.....\..\shuzizhong.hier_info
.....\..\shuzizhong.hif
.....\..\shuzizhong.map.cdb
.....\..\shuzizhong.map.hdb
.....\..\shuzizhong.map.qmsg
.....\..\shuzizhong.pre_map.cdb
.....\..\shuzizhong.pre_map.hdb
.....\..\shuzizhong.psp
.....\..\shuzizhong.rtlv.hdb
.....\..\shuzizhong.rtlv_sg.cdb
.....\..\shuzizhong.rtlv_sg_swap.cdb
.....\..\shuzizhong.sgdiff.cdb
.....\..\shuzizhong.sgdiff.hdb
.....\..\shuzizhong.sld_design_entry.sci
.....\..\shuzizhong.sld_design_entry_dsc.sci
.....\..\shuzizhong.syn_hier_info
.....\..\shuzizhong.tan.qmsg
.....\..\shuzizhong_cmp.qrpt
.....\decoder.v
.....\keyscan.v
.....\segscan.v
.....\shuzizhong.asm.rpt
.....\shuzizhong.cdf
.....\shuzizhong.done
.....\shuzizhong.fit.eqn
.....\shuzizhong.fit.rpt
.....\shuzizhong.fit.summary
.....\shuzizhong.flow.rpt
.....\shuzizhong.map.eqn
.....\shuzizhong.map.rpt
.....\shuzizhong.map.summary
.....\shuzizhong.pin
.....\shuzizhong.pof
.....\shuzizhong.qsf
.....\shuzizhong.sof
.....\shuzizhong.tan.rpt
.....\shuzizhong.tan.summary
.....\shuzizhong.v
.....\test6.qpf
.....\test6.qws
.....\db
clock
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