FPGA Verilog program , use for the board analyst and test . very helpfu

fp_prj
......\db
......\..\fp_verilog.ae.hdb
......\..\fp_verilog.asm.qmsg
......\..\fp_verilog.asm.rdb
......\..\fp_verilog.asm_labs.ddb
......\..\fp_verilog.cbx.xml
......\..\fp_verilog.cmp.cdb
......\..\fp_verilog.cmp.hdb
......\..\fp_verilog.cmp.kpt
......\..\fp_verilog.cmp.logdb
......\..\fp_verilog.cmp.rdb
......\..\fp_verilog.cmp.tdb
......\..\fp_verilog.cmp0.ddb
......\..\fp_verilog.db_info
......\..\fp_verilog.eco.cdb
......\..\fp_verilog.eda.qmsg
......\..\fp_verilog.fit.qmsg
......\..\fp_verilog.hier_info
......\..\fp_verilog.hif
......\..\fp_verilog.lpc.html
......\..\fp_verilog.lpc.rdb
......\..\fp_verilog.lpc.txt
......\..\fp_verilog.map.cdb
......\..\fp_verilog.map.hdb
......\..\fp_verilog.map.logdb
......\..\fp_verilog.map.qmsg
......\..\fp_verilog.pre_map.cdb
......\..\fp_verilog.pre_map.hdb
......\..\fp_verilog.rpp.qmsg
......\..\fp_verilog.rtlv.hdb
......\..\fp_verilog.rtlv_sg.cdb
......\..\fp_verilog.rtlv_sg_swap.cdb
......\..\fp_verilog.sgate.rvd
......\..\fp_verilog.sgate_sm.rvd
......\..\fp_verilog.sgdiff.cdb
......\..\fp_verilog.sgdiff.hdb
......\..\fp_verilog.sld_design_entry.sci
......\..\fp_verilog.sld_design_entry_dsc.sci
......\..\fp_verilog.smart_action.txt
......\..\fp_verilog.syn_hier_info
......\..\fp_verilog.tan.qmsg
......\..\fp_verilog.tis_db_list.ddb
......\..\fp_verilog.tmw_info
......\..\logic_util_heursitic.dat
......\..\prev_cmp_fp_verilog.asm.qmsg
......\..\prev_cmp_fp_verilog.eda.qmsg
......\..\prev_cmp_fp_verilog.fit.qmsg
......\..\prev_cmp_fp_verilog.map.qmsg
......\..\prev_cmp_fp_verilog.qmsg
......\..\prev_cmp_fp_verilog.tan.qmsg
......\fp_verilog.asm.rpt
......\fp_verilog.cdf
......\fp_verilog.done
......\fp_verilog.dpf
......\fp_verilog.eda.rpt
......\fp_verilog.fit.rpt
......\fp_verilog.fit.summary
......\fp_verilog.flow.rpt
......\fp_verilog.map.rpt
......\fp_verilog.map.summary
......\fp_verilog.pin
......\fp_verilog.pof
......\fp_verilog.qpf
......\fp_verilog.qsf
......\fp_verilog.qws
......\fp_verilog.tan.rpt
......\fp_verilog.tan.summary
......\fp_verilog.v
......\fp_verilog_nativelink_simulation.rpt
......\incremental_db
......\..............\compiled_partitions
......\..............\...................\fp_verilog.root_partition.map.kpt
......\..............\README
......\simulation
......\..........\modelsim
......\..........\........\fp_verilog.sft
......\..........\........\fp_verilog.vo
......\..........\........\fp_verilog.vt
......\..........\........\fp_verilog_modelsim.xrf
......\..........\........\fp_verilog_run_msim_rtl_verilog.do
......\..........\........\fp_verilog_v.sdo
......\..........\........\modelsim.ini
......\..........\........\msim_transcript
......\..........\........\rtl_work
......\..........\........\........\fp_verilog
......\..........\........\........\..........\verilog.prw
......\..........\........\........\..........\verilog.psm
......\..........\........\........\..........\_primary.dat
......\..........\........\........\..........\_primary.dbs
......\..........\........\........\..........\_primary.vhd
......\..........\........\........\fp_verilog_vlg_tst
......\..........\........\........\..................\verilog.prw
......\..........\........\........\..................\verilog.psm
......\..........\........\........\..................\_primary.dat
......\..........\........\........\..................\_primary.dbs
......\..........\........\........\..................\_primary.vhd
......\..........\........\........\_info
......\..........\........\........\_temp
......\..........\........\........\_vmake

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