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ele_lock

  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-04-20
  • Size : 836kb
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  • Author :刘****
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Introduction - If you have any usage issues, please Google them yourself
On Basys3 two buttons as inputs 0 and 1, only when the input is 01011 when, LED lights. Digital display to lose a few.
Packet file list
(Preview for download)


ele_lock\..hdi.isWriteableTest.4500.tmp
........\button\button.cache\wt\java_command_handlers.wdf
........\......\............\..\synthesis.wdf
........\......\............\..\synthesis_details.wdf
........\......\............\..\webtalk_pa.xml
........\......\.......runs\.jobs\vrs_config_1.xml
........\......\...........\synth_1\.vivado.begin.rst
........\......\...........\.......\.vivado.end.rst
........\......\...........\.......\.Vivado_Synthesis.queue.rst
........\......\...........\.......\button.dcp
........\......\...........\.......\button.tcl
........\......\...........\.......\button.vds
........\......\...........\.......\button_utilization_synth.pb
........\......\...........\.......\button_utilization_synth.rpt
........\......\...........\.......\gen_run.xml
........\......\...........\.......\htr.txt
........\......\...........\.......\ISEWrap.js
........\......\...........\.......\ISEWrap.sh
........\......\...........\.......\project.wdf
........\......\...........\.......\rundef.js
........\......\...........\.......\runme.bat
........\......\...........\.......\runme.log
........\......\...........\.......\runme.sh
........\......\...........\.......\vivado.jou
........\......\...........\.......\vivado.pb
........\......\.......srcs\sources_1\new\button.v
........\......\button.xpr
........\ele_lock.cache\wt\java_command_handlers.wdf
........\..............\..\synthesis.wdf
........\..............\..\synthesis_details.wdf
........\..............\..\webtalk_pa.xml
........\..............\..\xsim.wdf
........\.........hw\hw_1\hw.xml
........\.........runs\.jobs\vrs_config_1.xml
........\.............\.....\vrs_config_10.xml
........\.............\.....\vrs_config_11.xml
........\.............\.....\vrs_config_12.xml
........\.............\.....\vrs_config_13.xml
........\.............\.....\vrs_config_14.xml
........\.............\.....\vrs_config_15.xml
........\.............\.....\vrs_config_16.xml
........\.............\.....\vrs_config_17.xml
........\.............\.....\vrs_config_18.xml
........\.............\.....\vrs_config_19.xml
........\.............\.....\vrs_config_2.xml
........\.............\.....\vrs_config_20.xml
........\.............\.....\vrs_config_21.xml
........\.............\.....\vrs_config_22.xml
........\.............\.....\vrs_config_23.xml
........\.............\.....\vrs_config_24.xml
........\.............\.....\vrs_config_25.xml
........\.............\.....\vrs_config_26.xml
........\.............\.....\vrs_config_27.xml
........\.............\.....\vrs_config_28.xml
........\.............\.....\vrs_config_29.xml
........\.............\.....\vrs_config_3.xml
........\.............\.....\vrs_config_30.xml
........\.............\.....\vrs_config_31.xml
........\.............\.....\vrs_config_32.xml
........\.............\.....\vrs_config_33.xml
........\.............\.....\vrs_config_34.xml
........\.............\.....\vrs_config_35.xml
........\.............\.....\vrs_config_36.xml
........\.............\.....\vrs_config_37.xml
........\.............\.....\vrs_config_38.xml
........\.............\.....\vrs_config_4.xml
........\.............\.....\vrs_config_5.xml
........\.............\.....\vrs_config_6.xml
........\.............\.....\vrs_config_7.xml
........\.............\.....\vrs_config_8.xml
........\.............\.....\vrs_config_9.xml
........\.............\impl_1\.init_design.begin.rst
........\.............\......\.init_design.end.rst
........\.............\......\.opt_design.begin.rst
........\.............\......\.opt_design.end.rst
........\.............\......\.place_design.begin.rst
........\.............\......\.place_design.end.rst
........\.............\......\.stop.rst
........\.............\......\ele_lock.tcl
........\.............\......\ele_lock.vdi
........\.............\......\ele_lock_7340.backup.vdi
........\.............\......\ele_lock_clock_utilization_placed.rpt
........\.............\......\ele_lock_control_sets_placed.rpt
........\.............\......\ele_lock_drc_opted.rpt
........\.............\......\ele_lock_io_placed.rpt
.......
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