FPGA-based beamforming, including ad conversion, data storage and other parts. .

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....\BeamFormer
....\..........\3路信号分别相加.wcfg
....\..........\8路数据的读取.wcfg
....\..........\BeamFormer.gise
....\..........\BeamFormer.xise
....\..........\BeamFormerTop.jhd
....\..........\BeamFormerTop.sch
....\..........\BeamFormerTop.schbak
....\..........\BeamFormerTop.schcmd
....\..........\BeamFormerTop_summary.html
....\..........\beamformTop.cmd_log
....\..........\beamformTop.lso
....\..........\beamformTop.ngc
....\..........\beamformTop.ngr
....\..........\beamformTop.prj
....\..........\beamformTop.stx
....\..........\beamformTop.syr
....\..........\beamformTop.vhd
....\..........\beamformTop.xst
....\..........\beamformTop_envsettings.html
....\..........\beamformTop_summary.html
....\..........\beamformTop_xst.xrpt
....\..........\fuse.log
....\..........\fuse.xmsgs
....\..........\fuseRelaunch.cmd
....\..........\InterPolation.cmd_log
....\..........\InterPolation.lso
....\..........\InterPolation.prj
....\..........\InterPolation.stx
....\..........\InterPolation.vhd
....\..........\InterPolation.vhi
....\..........\InterPolation.xst
....\..........\ipcore_dir
....\..........\..........\adder1
....\..........\..........\adder1.asy
....\..........\..........\adder1.gise
....\..........\..........\adder1.ngc
....\..........\..........\adder1.sym
....\..........\..........\adder1.vhd
....\..........\..........\adder1.vho
....\..........\..........\adder1.xco
....\..........\..........\adder1.xise
....\..........\..........\......\doc
....\..........\..........\......\...\c_addsub_v11_0_readme.txt
....\..........\..........\......\...\c_addsub_v11_0_vinfo.html
....\..........\..........\......\...\ds214_addsub.pdf
....\..........\..........\adder1_flist.txt
....\..........\..........\adder1_xmdf.tcl
....\..........\..........\adder2
....\..........\..........\adder2.asy
....\..........\..........\adder2.gise
....\..........\..........\adder2.ncf
....\..........\..........\adder2.ngc
....\..........\..........\adder2.sym
....\..........\..........\adder2.vhd
....\..........\..........\adder2.vho
....\..........\..........\adder2.xco
....\..........\..........\adder2.xise
....\..........\..........\......\doc
....\..........\..........\......\...\c_addsub_v11_0_readme.txt
....\..........\..........\......\...\c_addsub_v11_0_vinfo.html
....\..........\..........\......\...\ds214_addsub.pdf
....\..........\..........\adder2_flist.txt
....\..........\..........\adder2_xmdf.tcl
....\..........\..........\adder3
....\..........\..........\adder3.asy
....\..........\..........\adder3.gise
....\..........\..........\adder3.ncf
....\..........\..........\adder3.ngc
....\..........\..........\adder3.sym
....\..........\..........\adder3.vhd
....\..........\..........\adder3.vho
....\..........\..........\adder3.xco
....\..........\..........\adder3.xise
....\..........\..........\......\doc
....\..........\..........\......\...\c_addsub_v11_0_readme.txt
....\..........\..........\......\...\c_addsub_v11_0_vinfo.html
....\..........\..........\......\...\ds214_addsub.pdf
....\..........\..........\adder3_flist.txt
....\..........\..........\adder3_xmdf.tcl
....\..........\..........\blk_mem_gen_ds512.pdf
....\..........\..........\blk_mem_gen_v6_2_readme.txt
....\..........\..........\coregen.cgp
....\..........\..........\coregen.log
....\..........\..........\create_adder1.tcl
....\..........\..........\create_adder2.tcl
....\..........\..........\create_adder3.tcl
....\..........\..........\create_mul16x8.tcl
....\..........\..........\create_ParallelAdd8.tcl
....\..........\..........\create_RAMRingIP.tcl
....\..........\..........\edit_adder1.tcl
....\..........\..........\edit_adder2.tcl
....\..........\..........\edit_mul16x8.tcl
....\..........\..........\edit_RAMRingIP.tcl
....\..........\..........\mul16x8
....\..........\..........\mul16x8.asy
....\..........\..........\mul16x8.gise
....\..........\..........\mul16x8.ngc
....\..........\..........\mul16x8.sym

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