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_Modelsim

  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-05-02
  • Size : 4.01mb
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Introduction - If you have any usage issues, please Google them yourself
modelsim reference software routines
Packet file list
(Preview for download)


05_DECODE_3_8\Modelsim\DECODE_3_8.cr.mti
.............\........\DECODE_3_8.mpf
.............\........\do.do
.............\........\do.do.bak
.............\........\vsim.wlf
.............\........\work\@d@e@c@o@d@e_3_8\verilog.asm
.............\........\....\................\_primary.dat
.............\........\....\................\_primary.vhd
.............\........\....\................_tb\verilog.asm
.............\........\....\...................\_primary.dat
.............\........\....\...................\_primary.vhd
.............\........\....\_info
.............\src\DECODE_3_8.v
.............\...\DECODE_3_8_tb.v
.6_DECODE_PRIORITY\Modelsim\DECODE_PRIORITY.cr.mti
..................\........\DECODE_PRIORITY.mpf
..................\........\do.do
..................\........\do.do.bak
..................\........\vsim.wlf
..................\........\work\@d@e@c@o@d@e_@p@r@i@o@r@i@t@y\verilog.asm
..................\........\....\.............................\_primary.dat
..................\........\....\.............................\_primary.vhd
..................\........\....\............................._tb\verilog.asm
..................\........\....\................................\_primary.dat
..................\........\....\................................\_primary.vhd
..................\........\....\_info
..................\src\DECODE_PRIORITY.v
..................\...\DECODE_PRIORITY_tb.v
.7_LATCH\Modelsim\do.do
........\........\LATCH_N.cr.mti
........\........\LATCH_N.mpf
........\........\vsim.wlf
........\........\work\@l@a@t@c@h_@n\verilog.asm
........\........\....\.............\_primary.dat
........\........\....\.............\_primary.vhd
........\........\....\...........tb\verilog.asm
........\........\....\.............\_primary.dat
........\........\....\.............\_primary.vhd
........\........\....\_info
........\src\LATCH_N.v
........\...\LATCH_N_tb.v
.8_FLIP_FLOP\Modelsim\do.do
............\........\FLIP_FLOP.cr.mti
............\........\FLIP_FLOP.mpf
............\........\vsim.wlf
............\........\work\@d@f@f_0\verilog.asm
............\........\....\........\_primary.dat
............\........\....\........\_primary.vhd
............\........\....\.f@l@i@p_@f@l@o@p\verilog.asm
............\........\....\.................\_primary.dat
............\........\....\.................\_primary.vhd
............\........\....\................._tb\verilog.asm
............\........\....\....................\_primary.dat
............\........\....\....................\_primary.vhd
............\........\....\.t@f@f_0\verilog.asm
............\........\....\........\_primary.dat
............\........\....\........\_primary.vhd
............\........\....\_info
............\src\FLIP_FLOP.v
............\...\FLIP_FLOP_tb.v
.9_COUNT\Modelsim\COUNT.cr.mti
........\........\COUNT.mpf
........\........\do.do
........\........\vsim.wlf
........\........\work\@c@o@u@n@t\verilog.asm
........\........\....\..........\_primary.dat
........\........\....\..........\_primary.vhd
........\........\....\.........._tb\verilog.asm
........\........\....\.............\_primary.dat
........\........\....\.............\_primary.vhd
........\........\....\_info
........\src\COUNT.v
........\...\COUNT_tb.v
10_SHIFT_REG\Modelsim\do.do
............\........\SHFIT_REG.cr.mti
............\........\SHFIT_REG.mpf
............\........\vsim.wlf
............\........\work\@s@h@i@f@t_@r@e@g\verilog.asm
............\........\....\.................\_primary.dat
............\........\....\.................\_primary.vhd
............\........\....\................._tb\verilog.asm
............\........\....\....................\_primary.dat
............\........\....\....................\_primary.vhd
............\........\....\_info
............\src\SHIFT_REG.v
............\...\SHIFT_REG_tb.v
.1_LFSR\Modelsim\do.do
.......\........\LFSR.cr.mti
.......\........\LFSR.mpf
.......\........\vsim.wlf
.......\........\work\@l@f@s@r\verilog.asm
.......\........\....\........\_primary.dat
.......\........\....\........\_primary.vhd
.......\......
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