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  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-05-02
  • Size : 523kb
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  • Author :franci*******
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Introduction - If you have any usage issues, please Google them yourself
Ejemplo sencillo de encender un led en VHDL
Packet file list
(Preview for download)


.lso
auto_project.ipf
auto_project2.ipf
auto_project2_xdb
.................\tmp
auto_project_xdb
................\tmp
BIESTABLE.prj
BIESTABLE.stx
BIESTABLE.xst
BIESTABLE_vhdl.prj
dcm1.vhd
dcm1.vhi
dcm1_arwz.ucf
estruct.cfi
estruct.gise
estruct.mcs
estruct.prm
estruct.sig
estruct.xise
impact.xsl
impact_impact.xwbt
ipcore_dir
..........\coregen.cgp
..........\coregen.log
..........\create_dcm1.tcl
..........\create_rom1.tcl
..........\dcm1.vhd
..........\dcm1.xaw
..........\dcm1_arwz.ucf
..........\dcm1_flist.txt
..........\edit_rom1.tcl
..........\rom1
..........\....\dist_mem_gen_v7_2_readme.txt
..........\....\doc
..........\....\...\dist_mem_gen_v7_2_vinfo.html
..........\....\...\pg063-dist-mem-gen.pdf
..........\....\example_design
..........\....\..............\rom1_exdes.ucf
..........\....\..............\rom1_exdes.vhd
..........\....\..............\rom1_exdes.xdc
..........\....\..............\rom1_prod_exdes.vhd
..........\....\implement
..........\....\.........\implement.bat
..........\....\.........\implement.sh
..........\....\.........\implement_synplify.bat
..........\....\.........\implement_synplify.sh
..........\....\.........\planAhead_ise.bat
..........\....\.........\planAhead_ise.sh
..........\....\.........\planAhead_ise.tcl
..........\....\.........\xst.prj
..........\....\.........\xst.scr
..........\....\simulation
..........\....\..........\functional
..........\....\..........\..........\simulate_mti.bat
..........\....\..........\..........\simulate_mti.do
..........\....\..........\..........\simulate_mti.sh
..........\....\..........\rom1_tb.vhd
..........\....\..........\rom1_tb_agen.vhd
..........\....\..........\rom1_tb_pkg.vhd
..........\....\..........\rom1_tb_stim_gen.vhd
..........\....\..........\rom1_tb_synth.vhd
..........\....\..........\timing
..........\....\..........\......\simulate_mti.bat
..........\....\..........\......\simulate_mti.do
..........\....\..........\......\simulate_mti.sh
..........\rom1.asy
..........\rom1.gise
..........\rom1.mif
..........\rom1.ncf
..........\rom1.ngc
..........\rom1.sym
..........\rom1.vhd
..........\rom1.vho
..........\rom1.xco
..........\rom1.xise
..........\rom1_flist.txt
..........\rom1_xmdf.tcl
..........\tmp
..........\...\_cg
..........\...\...\_dbg
..........\...\...\....\xil_12.in
..........\...\...\....\xil_12.out
..........\...\_xmsgs
..........\...\......\pn_parser.xmsgs
..........\...\......\xst.xmsgs
..........\xaw2vhdl.log
..........\xlnx_auto_0_xdb
..........\_xmsgs
..........\......\cg.xmsgs
..........\......\pn_parser.xmsgs
iseconfig
.........\estruct.projectmgr
.........\top.xreport
.........\TOP_1.xreport
MUX.prj
MUX.stx
MUX.xst
MUX_vhdl.prj
output.txt
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