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  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-05-04
  • Size : 580kb
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Introduction - If you have any usage issues, please Google them yourself
A simple ALU program designed to achieve the following functions: logic operations: AND, OR, NOT, XOR logical left, logical shift right arithmetic operations: addition, subtraction
Packet file list
(Preview for download)


my_alu\.lso
......\_ngo
......\....\netlist.lst
......\_xmsgs
......\......\map.xmsgs
......\......\netgen.xmsgs
......\......\ngdbuild.xmsgs
......\......\par.xmsgs
......\......\pn_parser.xmsgs
......\......\trce.xmsgs
......\......\xst.xmsgs
......\fuse.log
......\fuse.xmsgs
......\fuseRelaunch.cmd
......\ipcore_dir
......\iseconfig
......\.........\my_alu.projectmgr
......\.........\my_alu.xreport
......\isim.cmd
......\isim.log
......\isim
......\....\isim_usage_statistics.html
......\....\pn_info
......\....\temp
......\....\....\glbl.sdb
......\....\....\my_alu.sdb
......\....\....\test_alu.sdb
......\....\test_alu_isim_beh.exe.sim
......\....\.........................\isimcrash.log
......\....\.........................\ISimEngine-DesignHierarchy.dbg
......\....\.........................\isimkernel.log
......\....\.........................\libPortability.dll
......\....\.........................\netId.dat
......\....\.........................\test_alu_isim_beh.exe
......\....\.........................\tmp_save
......\....\.........................\........\_1
......\....\.........................\work
......\....\.........................\....\m_00000000000743494735_2429141254.c
......\....\.........................\....\m_00000000000743494735_2429141254.didat
......\....\.........................\....\m_00000000000743494735_2429141254.nt64.obj
......\....\.........................\....\m_00000000002168866868_2779603676.c
......\....\.........................\....\m_00000000002168866868_2779603676.didat
......\....\.........................\....\m_00000000002168866868_2779603676.nt64.obj
......\....\.........................\....\m_00000000004134447467_2073120511.c
......\....\.........................\....\m_00000000004134447467_2073120511.didat
......\....\.........................\....\m_00000000004134447467_2073120511.nt64.obj
......\....\.........................\....\test_alu_isim_beh.exe_main.c
......\....\.........................\....\test_alu_isim_beh.exe_main.nt64.obj
......\....\work
......\....\....\glbl.sdb
......\....\....\my_alu.sdb
......\....\....\test_alu.sdb
......\my_alu.bld
......\my_alu.cmd_log
......\my_alu.gise
......\my_alu.lso
......\my_alu.ncd
......\my_alu.ngc
......\my_alu.ngd
......\my_alu.ngr
......\my_alu.pad
......\my_alu.par
......\my_alu.pcf
......\my_alu.prj
......\my_alu.ptwx
......\my_alu.stx
......\my_alu.syr
......\my_alu.twr
......\my_alu.twx
......\my_alu.unroutes
......\my_alu.v
......\my_alu.xise
......\my_alu.xpi
......\my_alu.xst
......\my_alu_envsettings.html
......\my_alu_guide.ncd
......\my_alu_map.map
......\my_alu_map.mrp
......\my_alu_map.ncd
......\my_alu_map.ngm
......\my_alu_map.xrpt
......\my_alu_ngdbuild.xrpt
......\my_alu_pad.csv
......\my_alu_pad.txt
......\my_alu_par.xrpt
......\my_alu_summary.html
......\my_alu_summary.xml
......\my_alu_usage.xml
......\my_alu_xst.xrpt
......\netgen
......\......\synthesis
......\......\.........\my_alu_synthesis.nlf
......\......\.........\my_alu_synthesis.v
......\project_1
......\.........\import_ise_summary.txt
......\.........\project_1.cache
......\.........\...............\wt
......\.........\...............\..\webtalk_pa.xml
......\.........\project_1.hw
......\.........\............\project_1.lpr
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