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time_test

  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-05-04
  • Size : 536kb
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  • Author :猪*****
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Introduction - If you have any usage issues, please Google them yourself
Use 10M clock cycle design a single cycle waveform shape. This is written in Verilog
Packet file list
(Preview for download)


time_test\.lso
.........\_ngo
.........\....\netlist.lst
.........\_xmsgs
.........\......\map.xmsgs
.........\......\ngdbuild.xmsgs
.........\......\par.xmsgs
.........\......\pn_parser.xmsgs
.........\......\trce.xmsgs
.........\......\xst.xmsgs
.........\fuse.log
.........\fuse.xmsgs
.........\fuseRelaunch.cmd
.........\ipcore_dir
.........\iseconfig
.........\.........\time_test.projectmgr
.........\.........\time_test.xreport
.........\isim.cmd
.........\isim.log
.........\isim
.........\....\isim_usage_statistics.html
.........\....\pn_info
.........\....\temp
.........\....\....\glbl.sdb
.........\....\....\time_test.sdb
.........\....\....\time_test_2.sdb
.........\....\time_test_2_isim_beh.exe.sim
.........\....\............................\isimcrash.log
.........\....\............................\ISimEngine-DesignHierarchy.dbg
.........\....\............................\isimkernel.log
.........\....\............................\libPortability.dll
.........\....\............................\netId.dat
.........\....\............................\time_test_2_isim_beh.exe
.........\....\............................\tmp_save
.........\....\............................\........\_1
.........\....\............................\work
.........\....\............................\....\m_00000000000550808166_1063835092.c
.........\....\............................\....\m_00000000000550808166_1063835092.didat
.........\....\............................\....\m_00000000000550808166_1063835092.nt64.obj
.........\....\............................\....\m_00000000002096186097_3195384050.c
.........\....\............................\....\m_00000000002096186097_3195384050.didat
.........\....\............................\....\m_00000000002096186097_3195384050.nt64.obj
.........\....\............................\....\m_00000000004134447467_2073120511.c
.........\....\............................\....\m_00000000004134447467_2073120511.didat
.........\....\............................\....\m_00000000004134447467_2073120511.nt64.obj
.........\....\............................\....\time_test_2_isim_beh.exe_main.c
.........\....\............................\....\time_test_2_isim_beh.exe_main.nt64.obj
.........\....\work
.........\....\....\glbl.sdb
.........\....\....\time_test.sdb
.........\....\....\time_test_2.sdb
.........\time_test.bld
.........\time_test.cmd_log
.........\time_test.gise
.........\time_test.lso
.........\time_test.ncd
.........\time_test.ngc
.........\time_test.ngd
.........\time_test.ngr
.........\time_test.pad
.........\time_test.par
.........\time_test.pcf
.........\time_test.prj
.........\time_test.ptwx
.........\time_test.stx
.........\time_test.syr
.........\time_test.twr
.........\time_test.twx
.........\time_test.unroutes
.........\time_test.v
.........\time_test.xise
.........\time_test.xpi
.........\time_test.xst
.........\time_test_2.v
.........\time_test_2_beh.prj
.........\time_test_2_isim_beh.exe
.........\time_test_2_isim_beh.wdb
.........\time_test_2_stx_beh.prj
.........\time_test_envsettings.html
.........\time_test_guide.ncd
.........\time_test_map.map
.........\time_test_map.mrp
.........\time_test_map.ncd
.........\time_test_map.ngm
.........\time_test_map.xrpt
.........\time_test_ngdbuild.xrpt
.........\time_test_pad.csv
.........\time_test_pad.txt
.........\time_test_par.xrpt
.........\time_test_summary.html
.........\time_test_summary.xml
.........\time_test_usage.xml
.........\time_test_xst.xrpt
.........\webtalk_pn.xml
.........\xilinxsim.ini
.........\xlnx_auto_0_xdb
.........\...............\cst.xbcd
.........\xst
.........\...\dump.xst
.........\...\........\time_test.prj
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