This design uses 74160 period design digital clock, and the design of waveform simulation, the use of II QUARTUS design software, the design of the digital clock with the unit logic device to help

FPGA_JOW74160
.............\db
.............\..\FPGA_JOW74160.asm.qmsg
.............\..\FPGA_JOW74160.asm_labs.ddb
.............\..\FPGA_JOW74160.cbx.xml
.............\..\FPGA_JOW74160.cmp.bpm
.............\..\FPGA_JOW74160.cmp.cdb
.............\..\FPGA_JOW74160.cmp.ecobp
.............\..\FPGA_JOW74160.cmp.hdb
.............\..\FPGA_JOW74160.cmp.kpt
.............\..\FPGA_JOW74160.cmp.logdb
.............\..\FPGA_JOW74160.cmp.rdb
.............\..\FPGA_JOW74160.cmp.tdb
.............\..\FPGA_JOW74160.cmp0.ddb
.............\..\FPGA_JOW74160.cmp_merge.kpt
.............\..\FPGA_JOW74160.db_info
.............\..\FPGA_JOW74160.eco.cdb
.............\..\FPGA_JOW74160.eds_overflow
.............\..\FPGA_JOW74160.fit.qmsg
.............\..\FPGA_JOW74160.fnsim.cdb
.............\..\FPGA_JOW74160.fnsim.hdb
.............\..\FPGA_JOW74160.fnsim.qmsg
.............\..\FPGA_JOW74160.hier_info
.............\..\FPGA_JOW74160.hif
.............\..\FPGA_JOW74160.lpc.html
.............\..\FPGA_JOW74160.lpc.rdb
.............\..\FPGA_JOW74160.lpc.txt
.............\..\FPGA_JOW74160.map.bpm
.............\..\FPGA_JOW74160.map.cdb
.............\..\FPGA_JOW74160.map.ecobp
.............\..\FPGA_JOW74160.map.hdb
.............\..\FPGA_JOW74160.map.kpt
.............\..\FPGA_JOW74160.map.logdb
.............\..\FPGA_JOW74160.map.qmsg
.............\..\FPGA_JOW74160.map_bb.cdb
.............\..\FPGA_JOW74160.map_bb.hdb
.............\..\FPGA_JOW74160.map_bb.logdb
.............\..\FPGA_JOW74160.pre_map.cdb
.............\..\FPGA_JOW74160.pre_map.hdb
.............\..\FPGA_JOW74160.rtlv.hdb
.............\..\FPGA_JOW74160.rtlv_sg.cdb
.............\..\FPGA_JOW74160.rtlv_sg_swap.cdb
.............\..\FPGA_JOW74160.sgdiff.cdb
.............\..\FPGA_JOW74160.sgdiff.hdb
.............\..\FPGA_JOW74160.sim.cvwf
.............\..\FPGA_JOW74160.sim.hdb
.............\..\FPGA_JOW74160.sim.qmsg
.............\..\FPGA_JOW74160.sim.rdb
.............\..\FPGA_JOW74160.simfam
.............\..\FPGA_JOW74160.sld_design_entry.sci
.............\..\FPGA_JOW74160.sld_design_entry_dsc.sci
.............\..\FPGA_JOW74160.syn_hier_info
.............\..\FPGA_JOW74160.tan.qmsg
.............\..\FPGA_JOW74160.tis_db_list.ddb
.............\..\FPGA_JOW74160.tmw_info
.............\..\FPGA_JOW74160_global_asgn_op.abo
.............\..\prev_cmp_FPGA_JOW74160.asm.qmsg
.............\..\prev_cmp_FPGA_JOW74160.fit.qmsg
.............\..\prev_cmp_FPGA_JOW74160.map.qmsg
.............\..\prev_cmp_FPGA_JOW74160.qmsg
.............\..\prev_cmp_FPGA_JOW74160.tan.qmsg
.............\..\wed.wsf
.............\FPGA_JOW74160.asm.rpt
.............\FPGA_JOW74160.bdf
.............\FPGA_JOW74160.done
.............\FPGA_JOW74160.fit.rpt
.............\FPGA_JOW74160.fit.smsg
.............\FPGA_JOW74160.fit.summary
.............\FPGA_JOW74160.flow.rpt
.............\FPGA_JOW74160.map.rpt
.............\FPGA_JOW74160.map.summary
.............\FPGA_JOW74160.pin
.............\FPGA_JOW74160.pof
.............\FPGA_JOW74160.qpf
.............\FPGA_JOW74160.qsf
.............\FPGA_JOW74160.qws
.............\FPGA_JOW74160.sim.rpt
.............\FPGA_JOW74160.sof
.............\FPGA_JOW74160.tan.rpt
.............\FPGA_JOW74160.tan.summary
.............\FPGA_JOW74160.vwf
.............\incremental_db
.............\..............\compiled_partitions
.............\..............\...................\FPGA_JOW74160.root_partition.cmp.atm
.............\..............\...................\FPGA_JOW74160.root_partition.cmp.dfp
.............\..............\...................\FPGA_JOW74160.root_partition.cmp.hdbx
.............\..............\...................\FPGA_JOW74160.root_partition.cmp.kpt
.............\..............\...................\FPGA_JOW74160.root_partition.cmp.logdb
.............\..............\...................\FPGA_JOW74160.root_partition.cmp.rcf
.............\..............\...................\FPGA_JOW74160.root_partition.map.atm
.............\..............\...................\FPGA_JOW74160.root_partition.map.dpi
.............\..............\...................\FPGA_JOW74160.root_partition.map.hdbx
.............\..............\..........

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