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VHDL-FPGA-Verilog
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EDA
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VHDL-FPGA-Verilog
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Update : 2016-05-12
Size : 12kb
Downloaded :0次
Author :
Chen*****
About : Nobody
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Introduction - If you have any usage issues, please Google them yourself
Reedit
VHDL language with a variety of small modules, there is a revolving door, counters, registers, and so the cycle
Packet file list
(Preview for download)
EDA\100计时器.txt
...\64位计数器.txt
...\8位走马灯.doc
...\pmw.txt
...\tiaoshi.txt
...\二四译码器.txt
...\八段译码器.txt
...\十二进制计数器.txt
...\双向移位寄存器.txt
...\四位全加器.txt
...\四位减法.txt
...\奇偶校验.txt
...\延时左移循环寄存器.txt
...\循环显示13579.txt
...\移位寄存器.txt
...\而选一.txt
...\表决器.txt
...\转换成BCD码.txt
...\选择器.txt
...\选择计数.txt
...\高级计数器.txt
EDA
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