Design of FPGA system based on SHA-1 algorithm and DS28E01 encryption chip。

DS28E01_final
.............\Adder.vhd
.............\assignment_defaults.qdf
.............\CIII_SHA1.qarlog
.............\count.bsf
.............\count.vhd
.............\db
.............\..\add_sub_2qe.tdf
.............\..\add_sub_9se.tdf
.............\..\altsyncram_6os3.tdf
.............\..\altsyncram_6qk1.tdf
.............\..\altsyncram_8ls3.tdf
.............\..\altsyncram_als3.tdf
.............\..\altsyncram_aos3.tdf
.............\..\altsyncram_m2b2.tdf
.............\..\altsyncram_qns3.tdf
.............\..\altsyncram_t4b2.tdf
.............\..\altsyncram_vnk1.tdf
.............\..\cmpr_7dc.tdf
.............\..\cmpr_adc.tdf
.............\..\cmpr_bdc.tdf
.............\..\cmpr_ddc.tdf
.............\..\cntr_2di.tdf
.............\..\cntr_3di.tdf
.............\..\cntr_4di.tdf
.............\..\cntr_5di.tdf
.............\..\cntr_86j.tdf
.............\..\cntr_aai.tdf
.............\..\cntr_hbi.tdf
.............\..\cntr_hci.tdf
.............\..\cntr_ivi.tdf
.............\..\cntr_pci.tdf
.............\..\cntr_r7j.tdf
.............\..\decode_3pa.tdf
.............\..\decode_6pa.tdf
.............\..\decode_jri.tdf
.............\..\decode_trf.tdf
.............\..\logic_util_heursitic.dat
.............\..\mux_5lb.tdf
.............\..\mux_7lb.tdf
.............\..\mux_fpc.tdf
.............\..\mux_hpc.tdf
.............\..\mux_kjb.tdf
.............\..\mux_njb.tdf
.............\..\mux_vkb.tdf
.............\..\prev_cmp_top_level.asm.qmsg
.............\..\prev_cmp_top_level.fit.qmsg
.............\..\prev_cmp_top_level.map.qmsg
.............\..\prev_cmp_top_level.qmsg
.............\..\prev_cmp_top_level.restore.qmsg
.............\..\prev_cmp_top_level.sta.qmsg
.............\..\prev_cmp_top_level.tan.qmsg
.............\..\top_level.asm.qmsg
.............\..\top_level.asm.rdb
.............\..\top_level.asm_labs.ddb
.............\..\top_level.cbx.xml
.............\..\top_level.cmp.bpm
.............\..\top_level.cmp.cbp
.............\..\top_level.cmp.cdb
.............\..\top_level.cmp.ecobp
.............\..\top_level.cmp.hdb
.............\..\top_level.cmp.kpt
.............\..\top_level.cmp.logdb
.............\..\top_level.cmp.rdb
.............\..\top_level.cmp.tdb
.............\..\top_level.cmp0.ddb
.............\..\top_level.cmp2.ddb
.............\..\top_level.cmp_merge.kpt
.............\..\top_level.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
.............\..\top_level.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
.............\..\top_level.db_info
.............\..\top_level.eco.cdb
.............\..\top_level.eds_overflow
.............\..\top_level.fit.qmsg
.............\..\top_level.hier_info
.............\..\top_level.hif
.............\..\top_level.lpc.html
.............\..\top_level.lpc.rdb
.............\..\top_level.lpc.txt
.............\..\top_level.map.bpm
.............\..\top_level.map.cdb
.............\..\top_level.map.ecobp
.............\..\top_level.map.hdb
.............\..\top_level.map.kpt
.............\..\top_level.map.logdb
.............\..\top_level.map.qmsg
.............\..\top_level.map_bb.cdb
.............\..\top_level.map_bb.hdb
.............\..\top_level.map_bb.logdb
.............\..\top_level.pre_map.cdb
.............\..\top_level.pre_map.hdb
.............\..\top_level.restore.qmsg
.............\..\top_level.rtlv.hdb
.............\..\top_level.rtlv_sg.cdb
.............\..\top_level.rtlv_sg_swap.cdb
.............\..\top_level.sgdiff.cdb
.............\..\top_level.sgdiff.hdb
.............\..\top_level.sim.cvwf
.............\..\top_level.sim.hdb
.............\..\top_level.sim.qmsg

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