High Efficiency Video Coding(HEVC) is the currently developing video standard. In this article, a novel pipelined 2-D IDCT architecture based on HEVC is presented. By the analysis of the architecture design and adopting the area-saved and pipelined one, the Verilog HDL code is designed as well as logical simulation and performance analysis.

input_buf.v
matrix.v
memory.v
row_trf.v
ser_par.v
top.v
col_trf.v

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