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  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-06-02
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Graphic design QUARTUS II based on the input circuit
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基于QUARTUSII图形输入电路的设计\example1\exp1.asm.rpt
...............................\........\exp1.bdf
...............................\........\exp1.done
...............................\........\exp1.dpf
...............................\........\exp1.eda.rpt
...............................\........\exp1.fit.eqn
...............................\........\exp1.fit.rpt
...............................\........\exp1.fit.smsg
...............................\........\exp1.fit.summary
...............................\........\exp1.flow.rpt
...............................\........\exp1.map.eqn
...............................\........\exp1.map.rpt
...............................\........\exp1.map.summary
...............................\........\exp1.pin
...............................\........\exp1.pof
...............................\........\exp1.qpf
...............................\........\exp1.qsf
...............................\........\exp1.qws
...............................\........\exp1.sof
...............................\........\exp1.sta.rpt
...............................\........\exp1.sta.summary
...............................\........\exp1.tan.rpt
...............................\........\exp1.tan.summary
...............................\........\exp1_assignment_defaults.qdf
...............................\........\incremental_db\compiled_partitions\exp1.root_partition.map.kpt
...............................\........\..............\README
...............................\........\simulation\modelsim\exp1.sft
...............................\........\..........\........\exp1.vho
...............................\........\..........\........\exp1_8_1200mv_0c_vhd_slow.sdo
...............................\........\..........\........\exp1_8_1200mv_85c_vhd_slow.sdo
...............................\........\..........\........\exp1_min_1200mv_0c_vhd_fast.sdo
...............................\........\..........\........\exp1_modelsim.xrf
...............................\........\..........\........\exp1_vhd.sdo
...............................\........\timing\primetime\exp1.vho
...............................\........\......\.........\exp1_pt_vhd.tcl
...............................\........\......\.........\exp1_vhd.sdo
...............................\基于QUARTUSII图形输入电路的设计.docx
...............................\example1\incremental_db\compiled_partitions
...............................\........\simulation\modelsim
...............................\........\timing\primetime
...............................\........\db
...............................\........\incremental_db
...............................\........\simulation
...............................\........\timing
...............................\example1
基于QUARTUSII图形输入电路的设计
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