xilinxFPGAROM32* 1 primitive use, vivado engineering, simulation test file containing Testbench, add an address register, Anzhi can find the data you stored simulation glance, very good for beginners, verilog language to achieve this function.

Privite_rom_32\test.cache\wt\synthesis.wdf
..............\..........\..\webtalk_pa.xml
..............\..........\..\xsim.wdf
..............\.....sim\sim_1\behav\compile.bat
..............\........\.....\.....\compile.sh
..............\........\.....\.....\DEMO_TB.prj
..............\........\.....\.....\DEMO_TB.tcl
..............\........\.....\.....\DEMO_TB_behav.log
..............\........\.....\.....\DEMO_TB_behav.wdb
..............\........\.....\.....\xelab.log
..............\........\.....\.....\xelab.pb
..............\........\.....\.....\.sim.dir\DEMO_TB_behav\Compile_Options.txt
..............\........\.....\.....\........\.............\xsim.dbg
..............\........\.....\.....\........\.............\xsim.mem
..............\........\.....\.....\........\.............\xsim.reloc
..............\........\.....\.....\........\.............\xsim.rtti
..............\........\.....\.....\........\.............\xsim.svtype
..............\........\.....\.....\........\.............\xsim.type
..............\........\.....\.....\........\.............\xsim.xdbg
..............\........\.....\.....\........\.............\xsimcrash.log
..............\........\.....\.....\........\.............\xsimk.exe
..............\........\.....\.....\........\.............\xsimkernel.log
..............\........\.....\.....\........\xil_defaultlib\@d@e@m@o_@t@b.sdb
..............\........\.....\.....\........\..............\@r@o@m_32.sdb
..............\........\.....\.....\........\..............\glbl.sdb
..............\........\.....\.....\xsim.ini
..............\......rcs\sim_1\new\top_TB.v
..............\.........\.ources_1\new\demo.v
..............\test.xpr
..............\vivado.jou
..............\vivado.log
..............\vivado_4760.backup.jou
..............\vivado_4760.backup.log
..............\test.sim\sim_1\behav\xsim.dir\DEMO_TB_behav
..............\........\.....\.....\........\xil_defaultlib
..............\........\.....\.....\xsim.dir
..............\........\.....\behav
..............\......rcs\sim_1\new
..............\.........\.ources_1\new
..............\.....cache\compile_simlib
..............\..........\wt
..............\.....sim\sim_1
..............\......rcs\sim_1
..............\.........\sources_1
..............\.Xil
..............\test.cache
..............\test.sim
..............\test.srcs
Privite_rom_32

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