Pipeline CPU with forwarding and predict-not-taken

code1\alu_in_signal.v
.....\c_dat_mem.v
.....\c_dat_mem.veo
.....\c_dat_mem.vhd
.....\c_dat_mem.vho
.....\c_instr_mem.v
.....\c_instr_mem.veo
.....\c_instr_mem.vhd
.....\c_instr_mem.vho
.....\debug_out.v
.....\define.vh
.....\display.v
.....\displcd.v
.....\latch.v
.....\latch_EXE.v
.....\latch_ID.v
.....\latch_IF.v
.....\latch_MEM.v
.....\latch_MEN.v
.....\macro.vh
.....\Main.v
.....\Mips.v
.....\pbdebounce.v
.....\pipeline.bit
.....\Pipeline.v
.....\pipeline_control_hazard_detect.v
.....\pipeline_data_hazard_detect.v
.....\read_address.v
.....\SingleClock.v
.....\SingleControl.v
.....\single_add.v
.....\single_alu.v
.....\single_alu_ctr.v
.....\single_gpr.v
.....\single_mux.v
.....\single_pc.v
.....\single_pc_plus_4.v
.....\single_signext.v
.....\single_triple_mux.v
.....\top.ucf
.....\type_check.v
code1

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