Specifies synchronous reset, always sensitive to the table is just a clock edge signal only when the clock along to pick active level synchronous reset, the clock edge arrival time will be reset

syn_rst\asyn_rst\asyn_rst.prd
.......\........\asyn_rst.prj
.......\........\asyn_rst.v
.......\........\rev_1\asyn_rst.edn
.......\........\.....\asyn_rst.fse
.......\........\.....\asyn_rst.prf
.......\........\.....\asyn_rst.srm
.......\........\.....\asyn_rst.srr
.......\........\.....\asyn_rst.srs
.......\........\.....\asyn_rst.tlg
.......\........\.....\AutoConstraint_asyn_rst.sdc
.......\........\.....\generic.fse
.......\........\.....\generic.srd
.......\........\.....\syntmp\asyn_rst.msg
.......\........\.....\......\asyn_rst.plg
.......\........_syn_release\asyn_rst_syn_release.v
.......\syn_rst\rev_2\AutoConstraint_syn_rst.sdc
.......\.......\.....\generic.fse
.......\.......\.....\generic.srd
.......\.......\.....\syntmp\syn_rst.msg
.......\.......\.....\......\syn_rst.plg
.......\.......\.....\syn_rst.edn
.......\.......\.....\syn_rst.fse
.......\.......\.....\syn_rst.prf
.......\.......\.....\syn_rst.srm
.......\.......\.....\syn_rst.srr
.......\.......\.....\syn_rst.srs
.......\.......\.....\syn_rst.tlg
.......\.......\syntmp.msg
.......\.......\syn_rst.prd
.......\.......\syn_rst.prj
.......\.......\syn_rst.v
.......\示例说明.doc
.......\asyn_rst\rev_1\syntmp
.......\syn_rst\rev_2\par_1
.......\.......\.....\syntmp
.......\asyn_rst\rev_1
.......\syn_rst\rev_2
.......\.......\sim
.......\asyn_rst
.......\asyn_rst_syn_release
.......\source
.......\syn_rst
syn_rst

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