In general, CPU clock reading and writing will be introduced to the PLD, the author uses the CPU to read and write clock synchronized read and write registers, improve design reliability. Therefore, this model is the recommended way to read and write CPU registers modeling PLD

syn_wr\asyn_bad\asyn_bad.prd
......\........\asyn_bad.prj
......\........\decode.v
......\........\read_reg.v
......\........\..v_1\AutoConstraint_top.sdc
......\........\.....\decode.edn
......\........\.....\decode.fse
......\........\.....\decode.prf
......\........\.....\decode.srm
......\........\.....\decode.srr
......\........\.....\decode.srs
......\........\.....\decode.tlg
......\........\.....\generic.fse
......\........\.....\generic.srd
......\........\.....\syntmp\decode.msg
......\........\.....\......\decode.plg
......\........\top.v
......\........\write_reg.v
......\oe_edge\decode.v
......\.......\oe_edge.prd
......\.......\oe_edge.prj
......\.......\read_reg.v
......\.......\..v_2\AutoConstraint_top.sdc
......\.......\.....\generic.fse
......\.......\.....\generic.srd
......\.......\.....\syntmp\top.msg
......\.......\.....\......\top.plg
......\.......\.....\top.edn
......\.......\.....\top.fse
......\.......\.....\top.prf
......\.......\.....\top.srm
......\.......\.....\top.srr
......\.......\.....\top.srs
......\.......\.....\top.tlg
......\.......\top.v
......\.......\write_reg.v
......\syn_wr\decode.v
......\......\read_reg.v
......\......\..v_1\generic.fse
......\......\.....\generic.srd
......\......\.....\syntmp\top.msg
......\......\.....\......\top.plg
......\......\.....\top.edn
......\......\.....\top.fse
......\......\.....\top.prf
......\......\.....\top.srm
......\......\.....\top.srr
......\......\.....\top.srs
......\......\.....\top.tlg
......\......\syntmp.msg
......\......\syn_wr.prd
......\......\syn_wr.prj
......\......\top.v
......\......\write_reg.v
......\示例说明.doc
......\asyn_bad\rev_1\syntmp
......\oe_edge\rev_2\syntmp
......\syn_wr\rev_1\syntmp
......\asyn_bad\rev_1
......\oe_edge\rev_2
......\syn_wr\rev_1
......\asyn_bad
......\oe_edge
......\syn_wr
syn_wr

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