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  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-06-16
  • Size : 52kb
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  • Author :李***
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Introduction - If you have any usage issues, please Google them yourself
MT9v034 chip control procedures,Please feel free to download ,Please feel free to download
Packet file list
(Preview for download)


VIP_MT9V034_USB_RGB_EP4CE10_PP_KEY_752_480
..........................................\DELAY_RESET.v
..........................................\iic_com.v
..........................................\key_process.v
..........................................\PLL108.v
..........................................\Sdram_Control_4Port
..........................................\...................\command.v
..........................................\...................\command.v.bak
..........................................\...................\control_interface.v
..........................................\...................\control_interface.v.bak
..........................................\...................\PLL108.qip
..........................................\...................\Sdram_Control_4Port.v
..........................................\...................\Sdram_Control_4Port.v.bak
..........................................\...................\Sdram_FIFO.qip
..........................................\...................\Sdram_FIFO.v
..........................................\...................\Sdram_Params.h
..........................................\...................\Sdram_Params.h.bak
..........................................\...................\Sdram_PLL.ppf
..........................................\...................\Sdram_PLL.qip
..........................................\...................\Sdram_PLL.v
..........................................\...................\Sdram_PLL.v.bak
..........................................\...................\Sdram_rd_FIFO.qip
..........................................\...................\Sdram_rd_FIFO.v
..........................................\...................\Sdram_wr_FIFO.qip
..........................................\...................\Sdram_wr_FIFO.v
..........................................\...................\sdr_data_path.v
..........................................\...................\transcript
..........................................\VIP_USB_MT.qpf
..........................................\VIP_USB_MT.qsf
..........................................\VIP_USB_MT_TOP.v
..........................................\wr_fifo.v
..........................................\wr_sdram.v
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