ddr2 controller design for xilinx fpga, embedded IP soft core

ddr
...\86872581wb-ddr.zip
...\DDR2-verilog
...\DDR2-verilog.rar
...\............\9.2
...\............\...\altclklock.v
...\............\...\chart
...\............\...\.....\鍥?-16.bmp
...\............\...\.....\鍥?-17.bmp
...\............\...\.....\鍥?-19.bmp
...\............\...\.....\鍥?-20.bmp
...\............\...\.....\鍥?-22.bmp
...\............\...\.....\鍥?-23.bmp
...\............\...\.....\鍥?-26.bmp
...\............\...\.....\鍥?-27.bmp
...\............\...\ddr.cr.mti
...\............\...\ddr.mpf
...\............\...\ddr_Command.v
...\............\...\ddr_control_interface.v
...\............\...\ddr_data_path.v
...\............\...\ddr_sdram.v
...\............\...\ddr_sdram_tb.v
...\............\...\note.txt
...\............\...\Params.v
...\............\...\pll1.v
...\............\...\transcript
...\............\...\vsim.wlf
...\............\...\wave
...\............\...\....\ddr_command.bmp
...\............\...\....\ddr_control_interface.bmp
...\............\...\....\ddr_data_path.bmp
...\............\...\....\ddr_sdram.bmp
...\............\...\....\ddr_sdram_tb.bmp
...\............\...\work
...\............\...\....\altclklock
...\............\...\....\..........\verilog.asm
...\............\...\....\..........\_primary.dat
...\............\...\....\..........\_primary.vhd
...\............\...\....\ddr_command
...\............\...\....\...........\verilog.asm
...\............\...\....\...........\_primary.dat
...\............\...\....\...........\_primary.vhd
...\............\...\....\ddr_control_interface
...\............\...\....\.....................\verilog.asm
...\............\...\....\.....................\_primary.dat
...\............\...\....\.....................\_primary.vhd
...\............\...\....\ddr_data_path
...\............\...\....\.............\verilog.asm
...\............\...\....\.............\_primary.dat
...\............\...\....\.............\_primary.vhd
...\............\...\....\ddr_sdram
...\............\...\....\.........\verilog.asm
...\............\...\....\.........\_primary.dat
...\............\...\....\.........\_primary.vhd
...\............\...\....\ddr_sdram_tb
...\............\...\....\............\verilog.asm
...\............\...\....\............\_primary.dat
...\............\...\....\............\_primary.vhd
...\............\...\....\mt46v4m16
...\............\...\....\.........\verilog.asm
...\............\...\....\.........\_primary.dat
...\............\...\....\.........\_primary.vhd
...\............\...\....\pll1
...\............\...\....\....\transcript
...\............\...\....\....\verilog.asm
...\............\...\....\....\_primary.dat
...\............\...\....\....\_primary.vhd
...\............\...\....\_info
...\ddr_kongzhiqi
...\.............\ddr_kongzhiqi
...\.............\.............\source
...\.............\.............\......\ddr_ctrl.v
...\.............\.............\......\ddr_data.v
...\.............\.............\......\ddr_par.v
...\.............\.............\......\ddr_pll_orca.v
...\.............\.............\......\ddr_pll_orca_sp.v
...\.............\.............\......\ddr_sig.v
...\.............\.............\......\ddr_top.v
...\.............\.............\testbench
...\.............\.............\.........\ddr_tb.v
...\.............\.............\.........\stimulus.v
...\DDR_SDRAM_verilog.rar
...\wb-ddr
...\......\wb_ddr
...\......\......\.bzrignore
...\......\......\bench
...\......\......\.....\lac
...\......\......\.....\...\dp_ram.v
...\......\......\.....\...\lac.v
...\......\......\.....\...\uart.v
...\......\......\.....\wb_memtest.v
...\......\......\.....\wb_memtest2.v
...\......\......\.....\wb_memtest3.v
...\......\......\boards
...\......\......\......\xilinx-s3esk
...\......\......\......\............\Makefile
...\......\......\......\............\system.ucf
...\......\......\......\............\system.v
...\......\......\......\............\system.xst
...\......\......\......\............\system_sim.save

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