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uart(Verilog)

  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-06-26
  • Size : 11kb
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  • Author :飞***
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uart test code
Packet file list
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uart 源码 (Verilog)
...................\address_decode.v
...................\clock_divider.v
...................\control_operation.v
...................\cpu_interface.v
...................\serial_interface.v
...................\status_registers.v
...................\tester.v
...................\uart_tb.v
...................\uart_top.v
...................\xmit_rcv_control.v
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