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  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-06-28
  • Size : 259kb
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  • Author :ali el******
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temprature converter VHDL code
Packet file list
(Preview for download)


temp\device_usage_statistics.html
....\pepExtractor.prj
....\tc.bgn
....\tc.bit
....\tc.bld
....\tc.cmd_log
....\tc.drc
....\tc.lso
....\tc.ncd
....\tc.ngc
....\tc.ngd
....\tc.ngr
....\tc.pad
....\tc.par
....\tc.pcf
....\tc.prj
....\tc.ptwx
....\tc.spl
....\tc.stx
....\tc.sym
....\tc.syr
....\tc.twr
....\tc.twx
....\tc.ucf
....\tc.unroutes
....\tc.ut
....\tc.vhd
....\tc.vhi
....\tc.xpi
....\tc.xst
....\tc_guide.ncd
....\tc_map.map
....\tc_map.mrp
....\tc_map.ncd
....\tc_map.ngm
....\tc_map.xrpt
....\tc_ngdbuild.xrpt
....\tc_pad.csv
....\tc_pad.txt
....\tc_par.xrpt
....\tc_prev_built.ngd
....\tc_summary.xml
....\tc_usage.xml
....\tc_vhdl.prj
....\tc_xst.xrpt
....\temp.ise
....\temp.ntrc_log
....\temp.restore
....\...._xdb\cst.xbcd
....\........\tmp\ise\version
....\........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
....\........\...\...\............\..................\.........\HDProject_StrTbl
....\........\...\...\............\..................\__stored_object_table__
....\........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
....\........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
....\........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
....\........\...\...\............\................\................\dpm_project_main_StrTbl
....\........\...\...\............\................\__stored_objects__
....\........\...\...\............\................\__stored_objects___StrTbl
....\........\...\...\............\................\__stored_object_table__
....\........\...\...\............\................Gui\GuiProjectData
....\........\...\...\............\...................\GuiProjectData_StrTbl
....\........\...\...\..REGISTRY__\Autonym\regkeys
....\........\...\...\............\bitgen\regkeys
....\........\...\...\............\common\regkeys
....\........\...\...\............\.pldfit\regkeys
....\........\...\...\............\Cs\regkeys
....\........\...\...\............\dumpngdio\regkeys
....\........\...\...\............\ExpandedNetlistEngine\regkeys
....\........\...\...\............\fuse\regkeys
....\........\...\...\............\HierarchicalDesign\HDProject\regkeys
....\........\...\...\............\..................\regkeys
....\........\...\...\............\hprep6\regkeys
....\........\...\...\............\idem\regkeys
....\........\...\...\............\map\regkeys
....\........\...\...\............\netgen\regkeys
....\........\...\...\............\.gc2edif\regkeys
....\........\...\...\............\...build\regkeys
....\........\...\...\............\..dbuild\regkeys
....\........\...\...\............\par\regkeys
....\........\...\...\............\ProjectNavigator\regkeys
....\........\...\...\............\................Gui\regkeys
....\........\...\...\............\runner\regkeys
....\........\...\...\............\SrcCtrl\regkeys
....\........\...\...\............\.TE\bitgen\regkeys
....\........\...\...\............\...\map\regkeys
....\........\...\...\............\...\ngdbuild\regkeys
....\........\...\...\............\...\par\regkeys
....\........\...\...\............\...\regkeys
....\........\...\...\............\...\trce\regkeys
....\........\...\...\............\...\xst\regkeys
....\........\...\...\............\taengine\regkeys
....\........\...\...\............\.rce\regkeys
....\........\...\...\............\.sim\regkeys
....\........\...\...\............\vhpcomp\regkeys
....\........\...\...\............\.logcomp\regkeys
....\........\...\...\............\WebTalk\DesignDataCollection\regkeys
....\........\...\...\............\.......\regkeys
....\........\...\...\............\xpwr\regkeys
....\........\...\...\............\XSLTProcess\regkeys
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