Based verilog HDL state machine eight light water (a key control buttons turn left and turn right), the development environment Diamond 3.7 (64-bit) FPGA using LCMXO2-1200HC-4MG132C clock 25M development board: EEFOUCS little Step

state_led_one\.ncd_editor.ini
.............\.run_manager.ini
.............\.setting.ini
.............\.spreadsheet_view.ini
.............\.spread_sheet.ini
.............\impl1\.build_status
.............\.....\automake.log
.............\.....\hdla_gen_hierarchy.html
.............\.....\hdr_log
.............\.....\IBIS\state_led_one_impl1.ibs
.............\.....\impl1.xcf
.............\.....\message.xml
.............\.....\state_led_one_drc.log
.............\.....\state_led_one_impl1.alt
.............\.....\state_led_one_impl1.arearep
.............\.....\state_led_one_impl1.bgn
.............\.....\state_led_one_impl1.bit
.............\.....\....................dir\5_1.ncd
.............\.....\.......................\5_1.pad
.............\.....\.......................\5_1.par
.............\.....\.......................\5_1_par.asd
.............\.....\.......................\state_led_one_impl1.par
.............\.....\state_led_one_impl1.drc
.............\.....\state_led_one_impl1.ior
.............\.....\state_led_one_impl1.jed
.............\.....\state_led_one_impl1.log
.............\.....\state_led_one_impl1.lpf
.............\.....\state_led_one_impl1.lsedata
.............\.....\state_led_one_impl1.mrp
.............\.....\state_led_one_impl1.mt
.............\.....\state_led_one_impl1.ncd
.............\.....\state_led_one_impl1.ngd
.............\.....\state_led_one_impl1.p2t
.............\.....\state_led_one_impl1.p3t
.............\.....\state_led_one_impl1.pad
.............\.....\state_led_one_impl1.par
.............\.....\state_led_one_impl1.prf
.............\.....\state_led_one_impl1.pt
.............\.....\state_led_one_impl1.t2b
.............\.....\state_led_one_impl1.tw1
.............\.....\state_led_one_impl1.twr
.............\.....\state_led_one_impl1_bgn.html
.............\.....\state_led_one_impl1_iotiming.html
.............\.....\state_led_one_impl1_lattice.synproj
.............\.....\state_led_one_impl1_lse.twr
.............\.....\state_led_one_impl1_lse_lsetwr.html
.............\.....\state_led_one_impl1_map.asd
.............\.....\state_led_one_impl1_map.cam
.............\.....\state_led_one_impl1_map.hrr
.............\.....\state_led_one_impl1_map.ncd
.............\.....\state_led_one_impl1_mapvho.sdf
.............\.....\state_led_one_impl1_mapvho.vho
.............\.....\state_led_one_impl1_mapvo.sdf
.............\.....\state_led_one_impl1_mapvo.vo
.............\.....\state_led_one_impl1_mrp.html
.............\.....\state_led_one_impl1_pad.html
.............\.....\state_led_one_impl1_par.html
.............\.....\state_led_one_impl1_summary.html
.............\.....\state_led_one_impl1_trce.asd
.............\.....\state_led_one_impl1_tw1.html
.............\.....\state_led_one_impl1_twr.html
.............\.....\state_led_one_impl1_vho.sdf
.............\.....\state_led_one_impl1_vho.vho
.............\.....\state_led_one_impl1_vo.sdf
.............\.....\state_led_one_impl1_vo.vo
.............\.....\state_led_one_lse.twr
.............\.....\state_led_one_lse_lsetwr.html
.............\.....\state_led_one_prim.v
.............\.....\synthesis.log
.............\.....\synthesis_lse.html
.............\.....\xxx_lse_cp_file_list
.............\.....\xxx_lse_sign_file
.............\promote.xml
.............\reportview.xml
.............\state_led_one.ccl
.............\state_led_one.ldf
.............\state_led_one.lpf
.............\state_led_one.v
.............\state_led_one1.sty
.............\state_led_one_tcl.html
.............\................r.dir\pn160626162212.tcr
.............\.....................\pn160628101829.tcr
.............\testbench.v
.............\impl1\IBIS
.............\.....\state_led_one_impl1.dir
.............\impl1
.............\state_led_one_tcr.dir
state_led_one

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