FPGA HDLC interface protocol implementation using Verilog hdl

hdlc\db\altsyncram_2gu.tdf
....\..\altsyncram_gdu.tdf
....\..\alt_synch_pipe_0e8.tdf
....\..\alt_synch_pipe_hv7.tdf
....\..\alt_synch_pipe_iv7.tdf
....\..\alt_synch_pipe_sdb.tdf
....\..\a_gray2bin_47b.tdf
....\..\a_graycounter_836.tdf
....\..\a_graycounter_srb.tdf
....\..\a_graycounter_trb.tdf
....\..\a_graycounter_u9c.tdf
....\..\a_graycounter_v9c.tdf
....\..\dcfifo_2im1.tdf
....\..\dcfifo_ftj1.tdf
....\..\dffpipe_a09.tdf
....\..\dffpipe_b09.tdf
....\..\dffpipe_c09.tdf
....\..\dffpipe_c2e.tdf
....\..\dffpipe_lec.tdf
....\..\dffpipe_ngh.tdf
....\..\dffpipe_qe9.tdf
....\..\dffpipe_re9.tdf
....\..\hdlc_top.asm.qmsg
....\..\hdlc_top.asm_labs.ddb
....\..\hdlc_top.cbx.xml
....\..\hdlc_top.cmp.bpm
....\..\hdlc_top.cmp.cdb
....\..\hdlc_top.cmp.ecobp
....\..\hdlc_top.cmp.hdb
....\..\hdlc_top.cmp.logdb
....\..\hdlc_top.cmp.rdb
....\..\hdlc_top.cmp0.ddb
....\..\hdlc_top.cmp1.ddb
....\..\hdlc_top.db_info
....\..\hdlc_top.eco.cdb
....\..\hdlc_top.fit.qmsg
....\..\hdlc_top.hier_info
....\..\hdlc_top.hif
....\..\hdlc_top.map.bpm
....\..\hdlc_top.map.cdb
....\..\hdlc_top.map.ecobp
....\..\hdlc_top.map.hdb
....\..\hdlc_top.map.logdb
....\..\hdlc_top.map.qmsg
....\..\hdlc_top.map_bb.cdb
....\..\hdlc_top.map_bb.hdb
....\..\hdlc_top.map_bb.hdbx
....\..\hdlc_top.map_bb.logdb
....\..\hdlc_top.pre_map.cdb
....\..\hdlc_top.pre_map.hdb
....\..\hdlc_top.psp
....\..\hdlc_top.root_partition.cmp.atm
....\..\hdlc_top.root_partition.cmp.cfm
....\..\hdlc_top.root_partition.cmp.dfp
....\..\hdlc_top.root_partition.cmp.hdbx
....\..\hdlc_top.root_partition.cmp.logdb
....\..\hdlc_top.root_partition.cmp.rcf
....\..\hdlc_top.root_partition.map.atm
....\..\hdlc_top.root_partition.map.hdbx
....\..\hdlc_top.root_partition.map.info
....\..\hdlc_top.rpp.qmsg
....\..\hdlc_top.rtlv.hdb
....\..\hdlc_top.rtlv_sg.cdb
....\..\hdlc_top.rtlv_sg_swap.cdb
....\..\hdlc_top.sgate.rvd
....\..\hdlc_top.sgate_sm.rvd
....\..\hdlc_top.sgdiff.cdb
....\..\hdlc_top.sgdiff.hdb
....\..\hdlc_top.signalprobe.cdb
....\..\hdlc_top.sld_design_entry.sci
....\..\hdlc_top.sld_design_entry_dsc.sci
....\..\hdlc_top.smp_dump.txt
....\..\hdlc_top.sta.qmsg
....\..\hdlc_top.sta.rdb
....\..\hdlc_top.sta_cmp.6_slow.tdb
....\..\hdlc_top.syn_hier_info
....\..\hdlc_top.tis_db_list.ddb
....\..\hdlc_top.tmw_info
....\..\mux_gn7.tdf
....\..\prev_cmp_hdlc_top.asm.qmsg
....\..\prev_cmp_hdlc_top.fit.qmsg
....\..\prev_cmp_hdlc_top.map.qmsg
....\..\prev_cmp_hdlc_top.qmsg
....\..\prev_cmp_hdlc_top.sta.qmsg
....\FlagDetect.vhd
....\flag_ins.vhd
....\hdlc\hdlc_components_pkg.vhd
....\....\PCK_CRC16_D8.vhd
....\hdlc_top.asm.rpt
....\hdlc_top.done
....\hdlc_top.fit.rpt
....\hdlc_top.fit.smsg
....\hdlc_top.fit.summary
....\hdlc_top.flow.rpt
....\hdlc_top.map.rpt
....\hdlc_top.map.summary
....\hdlc_top.pin
....\hdlc_top.pof
....\hdlc_top.qpf
....\hdlc_top.qsf

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