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  • Category : VHDL-FPGA-Verilog
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  • Update : 2016-07-02
  • Size : 11.33mb
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  • Author :张***
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Introduction - If you have any usage issues, please Google them yourself
V5 DMA
Packet file list
(Preview for download)


xapp859\fpga
.......\....\chipscope_101_project
.......\....\.....................\trn_interface_demo.cdc
.......\....\.....................\trn_interface_demo.cpj
.......\....\implement
.......\....\.........\ml505
.......\....\.........\.....\bit_prom_files
.......\....\.........\.....\..............\impact_script
.......\....\.........\.....\..............\promgen_script.bat
.......\....\.........\.....\..............\run_impact.bat
.......\....\.........\.....\..............\xapp859_ml505.bit
.......\....\.........\.....\..............\xapp859_ml505.cfi
.......\....\.........\.....\..............\xapp859_ml505.mcs
.......\....\.........\.....\..............\xapp859_ml505.prm
.......\....\.........\.....\..............\xapp859_ml505.sig
.......\....\.........\.....\pcie_dma_top.xcf
.......\....\.........\.....\pcie_dma_top_plus_ml505.ucf
.......\....\.........\.....\xapp859.ise
.......\....\.........\ml555
.......\....\.........\.....\bit_prom_files
.......\....\.........\.....\..............\impact_script
.......\....\.........\.....\..............\promgen_script.bat
.......\....\.........\.....\..............\run_impact.bat
.......\....\.........\.....\..............\xapp859.bit
.......\....\.........\.....\..............\xapp859.cfi
.......\....\.........\.....\..............\xapp859.mcs
.......\....\.........\.....\..............\xapp859.prm
.......\....\.........\.....\..............\xapp859.sig
.......\....\.........\.....\pcie_dma_top.xcf
.......\....\.........\.....\pcie_dma_top_x8_plus.ucf
.......\....\.........\.....\xapp859.ise
.......\....\ip_cores
.......\....\........\coregen_memories
.......\....\........\................\a64_128_distram_fifo.ngc
.......\....\........\................\a64_128_distram_fifo.v
.......\....\........\................\a64_128_distram_fifo.veo
.......\....\........\................\a64_128_distram_fifo.xco
.......\....\........\................\a64_128_distram_fifo_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
.......\....\........\................\a64_128_distram_fifo_fifo_generator_v4_3_xst_1_vhdl.prj
.......\....\........\................\a64_128_distram_fifo_flist.txt
.......\....\........\................\a64_128_distram_fifo_readme.txt
.......\....\........\................\a64_128_distram_fifo_xmdf.tcl
.......\....\........\................\a64_64_distram_fifo.ngc
.......\....\........\................\a64_64_distram_fifo.v
.......\....\........\................\a64_64_distram_fifo.veo
.......\....\........\................\a64_64_distram_fifo.xco
.......\....\........\................\a64_64_distram_fifo_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
.......\....\........\................\a64_64_distram_fifo_fifo_generator_v4_3_xst_1_vhdl.prj
.......\....\........\................\a64_64_distram_fifo_flist.txt
.......\....\........\................\a64_64_distram_fifo_readme.txt
.......\....\........\................\a64_64_distram_fifo_xmdf.tcl
.......\....\........\................\addr_cntrl_fifo.ngc
.......\....\........\................\addr_cntrl_fifo.v
.......\....\........\................\addr_cntrl_fifo.veo
.......\....\........\................\addr_cntrl_fifo.xco
.......\....\........\................\addr_cntrl_fifo_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
.......\....\........\................\addr_cntrl_fifo_fifo_generator_v4_3_xst_1_vhdl.prj
.......\....\........\................\addr_cntrl_fifo_flist.txt
.......\....\........\................\addr_cntrl_fifo_readme.txt
.......\....\........\................\addr_cntrl_fifo_xmdf.tcl
.......\....\........\................\coregen_memories.cgp
.......\....\........\................\data_trn_mem_fifo.ngc
.......\....\........\................\data_trn_mem_fifo.v
.......\....\........\................\data_trn_mem_fifo.veo
.......\....\........\................\data_trn_mem_fifo.xco
.......\....\........\................\data_trn_mem_fifo_fifo_generator_v4_3_xst_1.ngc_xst.xrpt
.......\....\........\................\data_trn_mem_fifo_fifo_generator_v4_3_xst_1_vhdl.prj
.......\....\........\................\data_trn_mem_f
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