Based on FPGA MT9M034 image acquisition and displayed and TF card is routines, FPGA and SDRAM completed the acquisition of raw image and convert the RGB, and VGA display. NIOS completed the RGB image stored as a function of the BMP image and IIC CMOS configuration

CD1_MT9M034_DISPLAY_SAVE\FPGA_CODE\.sopc_builder\filters.xml
........................\.........\.............\install.ptf
........................\.........\.............\install2.ptf
........................\.........\.............\preferences.xml
........................\.........\CD1_MT9M034_DISPALY.v
........................\.........\CD1_MT9M034_DISPLAY.asm.rpt
........................\.........\CD1_MT9M034_DISPLAY.cdf
........................\.........\CD1_MT9M034_DISPLAY.done
........................\.........\CD1_MT9M034_DISPLAY.dpf
........................\.........\CD1_MT9M034_DISPLAY.fit.rpt
........................\.........\CD1_MT9M034_DISPLAY.fit.smsg
........................\.........\CD1_MT9M034_DISPLAY.fit.summary
........................\.........\CD1_MT9M034_DISPLAY.flow.rpt
........................\.........\CD1_MT9M034_DISPLAY.jdi
........................\.........\CD1_MT9M034_DISPLAY.map.rpt
........................\.........\CD1_MT9M034_DISPLAY.map.smsg
........................\.........\CD1_MT9M034_DISPLAY.map.summary
........................\.........\CD1_MT9M034_DISPLAY.pin
........................\.........\CD1_MT9M034_DISPLAY.pof
........................\.........\CD1_MT9M034_DISPLAY.qpf
........................\.........\CD1_MT9M034_DISPLAY.qsf
........................\.........\CD1_MT9M034_DISPLAY.qws
........................\.........\CD1_MT9M034_DISPLAY.sdc
........................\.........\CD1_MT9M034_DISPLAY.sof
........................\.........\CD1_MT9M034_DISPLAY.sta.rpt
........................\.........\CD1_MT9M034_DISPLAY.sta.summary
........................\.........\CD1_MT9M034_DISPLAY_assignment_defaults.qdf
........................\.........\CONTROL.v
........................\.........\cpu_0.ocp
........................\.........\cpu_0.sdc
........................\.........\cpu_0.v
........................\.........\cpu_0_bht_ram.mif
........................\.........\cpu_0_dc_tag_ram.mif
........................\.........\cpu_0_ic_tag_ram.mif
........................\.........\cpu_0_jtag_debug_module_sysclk.v
........................\.........\cpu_0_jtag_debug_module_tck.v
........................\.........\cpu_0_jtag_debug_module_wrapper.v
........................\.........\cpu_0_mult_cell.v
........................\.........\cpu_0_ociram_default_contents.mif
........................\.........\cpu_0_oci_test_bench.v
........................\.........\cpu_0_rf_ram_a.mif
........................\.........\cpu_0_rf_ram_b.mif
........................\.........\cpu_0_test_bench.v
........................\.........\db\CD1_MT9M034_DISPLAY.db_info
........................\.........\epcs_flash_controller_0.v
........................\.........\epcs_flash_controller_0_boot_rom.hex
........................\.........\greybox_tmp\cbx_args.txt
........................\.........\Image_RW_0.v
........................\.........\.P\DM9000A\DM9000A_IF_hw.tcl
........................\.........\..\.......\hdl\DM9000A_IF.v
........................\.........\..\Image_RW\Image_RW.v
........................\.........\..\........\Image_RW_hw.tcl
........................\.........\..\........\Image_RW_hw.tcl~
........................\.........\..\SRAM_16Bit_512K\hdl\SRAM_16Bit_512K.v
........................\.........\..\...............\SRAM_16Bit_512K_hw.tcl
........................\.........\jtag_uart_0.v
........................\.........\KEY.v
........................\.........\LED.v
........................\.........\MY_CODE\an.v
........................\.........\.......\CMOS_Capture.v
........................\.........\.......\CONTROL.v
........................\.........\.......\Curve_Averaging.v
........................\.........\.......\GAMA_COR\GamaCOR.v
........................\.........\.......\........\GamaCOR_B.mif
........................\.........\.......\........\GamaCOR_G.mif
........................\.........\.......\........\GamaCOR_R.mif
........................\.........\.......\........\GamaRAM_B.v
........................\.........\.......\........\GamaRAM_G.v
..............

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