verilogHDL language of uart module contains an internal baud rate generator, uart receive, uart made three sub-module, configured to support conventional baud rate, data bits, stop bits and parity bits, input operation clock 125M, the clock is not the same when needed change the baud rate generated code

UART
....\uart_baud_tick_gen.v
....\uart_rx.v
....\uart_top_block.v
....\uart_tx.v

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